Hi,
I have a question about or1200_dmmu_tlb.v. Why the TLB are implemented with register, not the real SPRAM. The l.mfspr instruction is two cycle. And the commend in the verilog code is that: "// to read from ITLB/DTLB (sync RAMs)". IF the TLB is not RAMs, l.mfspr's two cycle will make no sense.

Another question: If the TLB are implemented with RAMs, and if there is debug access to sprs, when the executing instruction is l.mfspr from TLB. A wrong value will get, because after debug access, the two cycle of the l.mfspr can't work as usual, the read address of sprs can't change in time.