Hello fellow OpenRisc'ers,

Please forgive me if this has already been discussed (and please point me to an efficient search of archives...?).

In file or1200_iwb_biu.v, it seems that 'repeated_access' is triggering a spurious 2nd ack to the execution unit.

I am simulating or1200 with the memory controller in Questa 10.0b. The MC returns only one ack for the first memory read, as expected. However, the iwb_biu is creating a 2nd pulse on biu_ack_o based on the signal 'repeated_access', thus causing the pipeline to step (unfreeze) erroneously.

Could someone please explain the reason for this behavior, and whether that is as expected or not?

BTW, I have the MC configured at reset to use SRAM, to minimize the setup in order to get things working quickly.

Thanks and best regards,
Dave Hollenbeck

Would you be able to post a waveform?

You're sure the slave's ack is asserted for just the single cycle coming back from the memory controller?

I'll work on Q1, but for Q2, yes, only 1 ack for one cycle at the iwb interface. The model is configured with no cache.

One thing I am also noticing is some glitches. I'll have to remind myself but I think maybe one of the freeze signals was exhibiting this.

Thanks,
Dave

Attached is a waveform window showing the double ack. It stems from the signal repeated_access, which I don't understand after trying to trace the logic back. Coincidentally there is a glitch on repeated_access. There are some additional signals at the bottom from the memory controller, as I was trying to track down the strange delay in the iwb_ack signal. Haven't found it.

Any suggestions on where to look or explanations of intended or actual behavior would be greatly appreciated.

To recap, this is a module with only the or1200 and a memory controller. No MMUs, no cache, and no QMEM. Right after reset.

Thanks and regards,
Dave

From where have you acquired your or1200 version?
It looks old from the fact that the problem causing
signal 'repeated_access' doesn't exists in the current or1200_iwb_biu.v.

http://opencores.org/websvn,filedetails?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1200%2Frtl%2Fverilog%2For1200_iwb_biu.v

I downloaded from the project browser, then or1200-rel1. My preference was for a stable release instead of the bleeding edge from svn. How drastically is the RTL changing? Is there a snapshot that is a better candidate than the one I downloaded?

Thanks much,
Dave

I'd say that the one in SVN is the most stable at the moment,
I think all the snapshots that are available have some nasty bugs that are fixed
in current SVN.

Stefan