Hello again, and thanks for your patience as I learn this architecture and design while bringing it up in the verilog simulator.

I'm trying to invalidate the Instruction Cache as part of the startup code. However I'm not sure I'm doing it the recommended way. I'm using

l.mtspr r0,r6,0x2002 (hex C080_3002)

in a loop to invalidate all lines in the cache. Where is the ICBIR register in the RTL? Is the proper method to write to ICBIR?

However, I don't see any code in the or1200_sprs.v or or1200_ic*.v files that handle this instruction.

Sorry if this is an ignorant question.

Thanks and regards,
Dave

The write to the cache block invalidate registers gets decoded and put through to the caches, where they trigger a clearing of the valid bit in the tag ram for the line/block corresponding to the address you want to invalidate.

Thanks, I see that now. What was confusing me also was the collision at the Icache that inadvertently triggers a miss fill. There appears to be no pipeline freeze when the Icache tag is invalidated through the mtspr instruction. Is that true? I hacked the RTL to wedge one in and the behavior looks much better.

BTW, I have caches configured but no MMUs, not that I think that should matter...

Thanks again,
Dave