I recently downloaded the latest version from websvn. In or1200_wb_biu.v, the two defines
`define OR1200_WB_B3
and
`define OR1200_WB_CAB
are only partially implemented. If I undefine either of them the file will not compile because there are still many uses of the now-undefined ports.

Is it possible to build this design without the B3 or CAB features? The -rel1 version seemed to behave pretty well without it.

Thanks and regards,
Dave

Hi Dave,

The CAB stuff was from earlier revisions of the Wishbone standard. It's no longer used. The B3-related signals are what are used these days to implement burst accesses over the bus.

It's possible to make the processor look like it's only performing non-burst (aka "classic" cycles) by not connecting its cycle type indicator (CTI) or burst type (BTE) signals to the bus/slaves. So, to compile, you'll need to keep the B3 option enabled, and the processor will function fine without the wishbone slaves its accessing supporting the bursting operations.

Cleaning out the CAB stuff is probably something that should be done to help avoid confusion.