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Are the pipe stages architected?
by VlsiDave on Oct 31, 2011 		VlsiDave
Posts: 16
Joined: Jun 28, 2011
Last seen: Dec 20, 2011
Hi,

Is there an architectural spec for the cpu pipeline? Certainly it describes the delay slot of a branch. Even if not architected, is there a document or diagram of it, possibly with signals assigned to the various pipe stages?

Thanks and regards,
Dave
RE: Are the pipe stages architected?
by julius on Oct 31, 2011 		julius
Posts: 363
Joined: Jul 1, 2008
Last seen: May 17, 2021
Not to my knowledge. The RTL is the documentation, unfortunately.
RE: Are the pipe stages architected?
by julius on Oct 31, 2011 		julius
Posts: 363
Joined: Jul 1, 2008
Last seen: May 17, 2021
But I recall that the OR1200 was largely based on the worked DLX pipeline example in the Hennessy and Patterson text, Computer Architecture: A Quantitative Approach.
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