Hello,
I have tried to port orpsoc2 to a 8Mbytes' sdram board, but I failed, so anyone who has succeed finishing this work, can you shared your experience
with me?
regards

Could you describe in more detail what the problem is? Do you need to have a new memory controller or change an existing controller to use 8MB? Which board is it?

You need to change the size of row and column address vectors.
In the actel board build branch in versatile_mem_ctrl you need to change this.
Easiest way would be to do like this
In the file versatile_mem_ctrl.v (which is a preprocessed file) replace the content from
the file sdr_fsm_16.v with the file found in rtl/verilog/fsm_16_sdr.v

For a micron 4M16 set defines like this
`define BA_SIZE 2
`define ROW_SIZE 12
`define COL_SIZE 8

Hope this explains what you need to do, if not let me know

/Michael Unneback

Hello,
It's de0_nano port from stefan's git://openrisc.net/stefan/orpsoc,here is the mail talks with stefan,but I still can solve the problem:
On Wed, Nov 09, 2011 at 10:58:20AM +0800, liunx wrote:
> � 2011年11�07� 23:41, Stefan Kristiansson ��:
>> On 11/07/2011 05:10 PM, liunx wrote:
>>> On Mon, 2011-11-07 at 10:58 +0200, Stefan Kristiansson wrote:
>>>> On Mon, Nov 07, 2011 at 04:38:03PM +0800, liunx wrote:
>>>>> � 2011年11�07� 16:02, Stefan Kristiansson ��:
>>>>>> On Mon, Nov 07, 2011 at 03:09:20PM +0800, liunx wrote:
>>>>>>> Hi,
>>>>>>> Thanks for your reply.
>>>>>>> 1. I have a K4S641632H-UC(L)75 8Mbytes sdram.
>>>>>>> 2. I tried the rtl simulation, but I just got a stuck
>>>>>>> result like this:
>>>>>>> $ make rtl-test MGC_NO_VOPT=1
>>>>>>> ...
>>>>>>> # 1
>>>>>>> # run -all
>>>>>>> #
>>>>>>> # * Starting simulation of design RTL.
>>>>>>> # * Test: or1200-simple
>>>>>>> #
>>>>>>> # Note : Cyclone IV E PLL locked to incoming clock
>>>>>>> # Time: 90.0 ns Instance: orpsoc_testbench.dut.clkgen0.pll0.altpll_component.cycloneiii_pll.pll3
>>>>>>>
>>>>>>> # Note : Cyclone IV E PLL was reset
>>>>>>> # Time: 660.0 ns Instance: orpsoc_testbench.dut.clkgen0.pll0.altpll_component.cycloneiii_pll.pll3
>>>>>>>
>>>>>>> # Note : Cyclone IV E PLL locked to incoming clock
>>>>>>> # Time: 1390.0 ns Instance: orpsoc_testbench.dut.clkgen0.pll0.altpll_component.cycloneiii_pll.pll3
>>>>>>>
>>>>>>>
>>>>>>> It stuck here, never exit.
>>>>>> Ok, do you think you could create a VCD for me to look at?
>>>>>> $ make rtl-test MGC_NO_VOPT=1 VCD=1
>>>>>>
>>>>>>
>>>>>>> All this work did in the de0_nano directory, I also try to run the
>>>>>>> simulation in the
>>>>>>> de2_115 directory, but I failed with this result:
>>>>>>> ...
>>>>>>> # 6.6d
>>>>>>>
>>>>>>> # vsim -L lib_backend -do {set StdArithNoWarnings 1; run -all; exit}
>>>>>>> -c -quiet -suppress 8598 orpsoc_testbench
>>>>>>> # ALTERA version supports only a single HDL
>>>>>>> # ** Fatal: (vsim-3039) /home/liunx/Work/Eda/fpga/orpsoc/new/orpsoc/boards/altera/de2_115/sim/run/../../rtl/verilog/orpsoc_top/orpsoc_top.v(1059):
>>>>>>> Instantiation of 'altera_virtual_jtag' failed.
>>>>>>>
>>>>>>> I guess the web version does not support making both vhdl and
>>>>>>> verilog hdl in the same time.
>>>>>>> I may need some rtl simulation tutors.
>>>>>>> regards
>>>>>>>
>>>>>> I'm going to purge that single .vhdl file and make it a verilog file,
>>>>>> there's no reason to keep it in vhdl.
>>>>>>
>>>>>> What is strange is that you don't get that error on the
>>>>>> de0_nano board,
>>>>>> it should be the same.
>>>>>> Have you enabled the advanced debug sys in the de0 nano board
>>>>>> (it is off by default)?
>>>>>>
>>>>>>
>>>>>> Stefan
>>>>> Yes, I had do this work,
>>>>>
>>>>> //`define LEGACY_DBG_IF
>>>>> `define ADV_DBG_IF
>>>>>
>>>>> // JTAG TAP defines
>>>>> //`define GENERIC_JTAG_TAP
>>>>> `define ALTERA_JTAG_TAP
>>>>>
>>>>> `define VERSATILE_SDRAM
>>>>> //`define RAM_WB
>>>>>
>>>>> that's not a problem, but what about my sdram, is it fit for the
>>>>> wb_versatile_mem_ctrl ? And how about the rtl simulation result,
>>>>> does it work?
>>>>> regards
>>>> I think that SDRAM chip should work with wb_sdram_ctrl,
>>>> no such thing as wb_verstaile_mem_ctrl exists.
>>>> (wb_sdram_ctrl is an replacement to versatile_mem_ctrl,
>>>> and the reason for making it was that versatile_mem_ctrl is
>>>> extremely slow)
>>>>
>>>> As for the simulation, do you have a model for that chip?
>>>>
>>>> Stefan
>>> Hi,
>>> Sorry, I don't have the model for that chip, but you may right, "that
>>> SDRAM chip should work with wb_sdram_ctrl", I tried it in my fpga board,
>>> when I just modify this:
>>>
>>> wb_sdram_ctrl
>>> #(
>>> .CLK_FREQ_MHZ (100), // sdram_clk freq in MHZ
>>> .POWERUP_DELAY (200), // power up delay in us
>>> .WB_PORTS (3), // Number of wishbone ports
>>> .ROW_WIDTH (12), // Row width
>>> .COL_WIDTH (8), // Column width
>>> .BA_WIDTH (2), // Ba width
>>> .tCAC (2), // CAS Latency
>>> .tRAC (5), // RAS Latency
>>> .tRP (2), // Command Period (PRE to ACT)
>>> .tRC (7), // Command Period (REF to
>>> REF / ACT to ACT)
>>> .tMRD (2) // Mode Register Set To
>>> Command Delay time
>>> )
>>> do the adv_jtag_bridge self-tests, it's failed!
>>> But then I changed the clock of sdram to 50mhz, (I also changed the pll
>>> settings), OK, the self-tests to sdram passed!
>>> (the output)
>>> ...
>>> liunx@gentoo
>>> ~/Work/Fpga/orpsoc/new/orpsoc/boards/altera/de0_nano/syn/quartus/run $
>>> adv_jtag_bridge -l 0:10 -t usbblaster
>>> Found Altera USB-Blaster
>>> Found Altera USB-Blaster
>>> firmware version = 0x0004 (4)
>>> Enumerating JTAG chain...
>>>
>>> Devices on JTAG chain:
>>> Index Name ID Code IR Length
>>> ----------------------------------------------------------------
>>> 0: (unknown) 0x020B30DD -1
>>>
>>> Target device 0, JTAG ID = 0x020b30dd
>>> *** Doing self-test ***
>>> Stall or1k - CPU(s) stalled.
>>> SRAM test:
>>> expected 11112222, read 11112222
>>> expected 33334444, read 33334444
>>> expected 55556666, read 55556666
>>> expected 77778888, read 77778888
>>> expected 9999aaaa, read 9999aaaa
>>> expected bbbbcccc, read bbbbcccc
>>> expected ddddeeee, read ddddeeee
>>> expected ffff0000, read ffff0000
>>> expected dedababa, read dedababa
>>> SRAM test passed
>>> Testing CPU0 (or1k) - writing instructions
>>> Setting up CPU0
>>> Starting CPU0!
>>> Read npc = 00000010 ppc = 00000028 r1 = 00000005
>>> Expected npc = 00000010 ppc = 00000028 r1 = 00000005
>>> Read npc = 00000028 ppc = 00000024 r1 = 00000008
>>> Expected npc = 00000010 ppc = 00000028 r1 = 00000008
>>> Read npc = 00000024 ppc = 00000020 r1 = 0000000b
>>> Expected npc = 00000028 ppc = 00000024 r1 = 0000000b
>>> Read npc = 00000024 ppc = 00000028 r1 = 0000000b
>>> Expected npc = 00000024 ppc = 00000020 r1 = 00000018
>>> Read npc = 00000024 ppc = 00000020 r1 = 0000000b
>>> Expected npc = 00000020 ppc = 0000001c r1 = 00000031
>>> Read npc = 00000020 ppc = 0000001c r1 = 0000000c
>>> Expected npc = 00000024 ppc = 00000020 r1 = 00000032
>>> Read npc = 00000020 ppc = 00000024 r1 = 0000000c
>>> Expected npc = 00000014 ppc = 00000010 r1 = 00000063
>>> Read npc = 00000020 ppc = 00000024 r1 = 0000000c
>>> Expected npc = 00000028 ppc = 00000024 r1 = 00000065
>>> Read npc = 00000010 ppc = 00000028 r1 = 00000016
>>> Expected npc = 00000010 ppc = 00000028 r1 = 000000c9
>>> result = deadd85d
>>> Self-test FAILED *** Bailing out!
>>> ...
>>> But wait, when I happy to download a program to the memory, it failed
>>> again:
>>> (debugger side)
>>> ...
>>> (gdb) target remote:9999
>>> Remote debugging using :9999
>>> 0x00000020 in ?? ()
>>> (gdb) load
>>> Loading section .reset, size 0x190 lma 0x0
>>> Loading section .vectors, size 0xe1c lma 0x200
>>> Loading section .text, size 0x1408 lma 0x1200
>>> Remote connection closed
>>> (gdb)
>>> ...
>>> (adv_jtag_bridge side)
>>> liunx@gentoo
>>> ~/Work/Fpga/orpsoc/new/orpsoc/boards/altera/de0_nano/syn/quartus/run $
>>> adv_jtag_bridge -l 0:10 usbblaster
>>> Found Altera USB-Blaster
>>> Found Altera USB-Blaster
>>> firmware version = 0x0004 (4)
>>> Enumerating JTAG chain...
>>>
>>> Devices on JTAG chain:
>>> Index Name ID Code IR Length
>>> ----------------------------------------------------------------
>>> 0: (unknown) 0x020B30DD -1
>>>
>>> Target device 0, JTAG ID = 0x020b30dd
>>> No watchpoint hardware found, HWP server not starting
>>> HWP server listening on host gentoo (0.0.0.0), port 9928, address family
>>> IPv4
>>> JTAG bridge ready!
>>> HWP server thread running!
>>> CRC ERROR! match bit after write is 0 (computed CRC 0x9837d217)Retry
>>> count exceeded! Abort!
>>>
>>> Does the adv_jtag_bridge tell lies? Or something else wrong?
>>>
>>> Lei
>>>
>>>
>>>
>> yes, I get that too sometimes,
>> the adv-jtag bridge is a bit flaky in combination with the de0 nano board
>> (and obviously with your board too)
>> One guy actually disabled the crc check in the source to solve that,
>> it seemed to work ok without it.
>>
>> When I get time I will take a good look at why it does that sometimes.
>>
>> You can try doing that or just reconnect until the loading succeeds,
>> or if you have a debugger similar to the orsoc debugger you could
>> try using that.
>> That have been working reliable for me.
>>
>> Stefan
> Hi,
> Thanks for your advise, but it's may not a bit flaky, I tried to
> disable the crc check, but I got the bus error, finally.
> So, I recover the pll to 100MHZ again, of course, the
> adv_jtag_bridge test failed, but I can connect the bridge with
> debugger and download the binary into memory, no CRC EEROR! So I
> guess the original configuration --should-- work, and I tried to
> tweak the parameters, but it still did not work.:'(
> You may say, OK, you can download the binary into memory, why not
> run it? Unluckily, when I try this operations:
> (gdb) set $pc=0x100
> Value being assigned to is no longer active.
> Sometimes it can pass this step, but when I type:
> (gdb) c
> It failed with Illegal instructions.
> I've no ideas, now,can you give me some tips?:-)
> regards.
>
> Lei
>
I still got a feeling it's more of a problem with the adv_debug_sys
than the SDRAM controller
(although I'm not saying the saying the SDRAM controller is perfect (yet))
Can you load your program by any other mean than with the adv_debug_sys?
What program are you trying to load, is it confirmed that it should work?

Stefan

Any tips?
regards

Lei