Hi, I'm trying to simulate the minsoc (RC1.0) design with modelsim and VPI, but I can't get adv_jtag_bridge work. And I'm using the UART example. Here some settings: In minsoc_bench_defines.v: - GENERIC_FPGA enabled - MEMORY_MODEL enabled - VPI_DEBUG enabled - INITIALIZE_MEMORY_MODEL disabled - START_UP disabked - TEST_UART and TEST_ETHERNET disabled in minsoc_defines.v: - GENERIC_TAP enabled - GENERIC_MEMORY enabled in or1200_defines.v - no data-cache and no instruction cache The command (from sim/run/start_server) adv_jtag_bridge.exe -x 0 -c 0x8 -l 0:4 vpi gives me the following errors: Devices on JTAG chain: Index Name ID Code IR Length ------------------------------------------------- 0: 0x149511C3 -1 Target device 0, JTAG ID = 0x149511c3 JSP server listening on host winxp (0.0.0.0), port 9944, address family IPv4 JSP server thread running! Burst read timed out Retry count exceeded in burst read! ERROR reading DCR 0 at startup! 'max retries' Burst read timed out Retry count exceeded in burst read! ERROR reading DCR 1 at startup! 'max retries' Burst read timed out Retry count exceeded in burst read! ERROR reading DCR 2 at startup! 'max retries' Burst read timed out Retry count exceeded in burst read! ERROR reading DCR 3 at startup! 'max retries' Burst read timed out Retry count exceeded in burst read! ERROR reading DCR 4 at startup! 'max retries' Burst read timed out Retry count exceeded in burst read! ERROR reading DCR 5 at startup! 'max retries' Burst read timed out Retry count exceeded in burst read! ERROR reading DCR 6 at startup! 'max retries' Burst read timed out Retry count exceeded in burst read! ERROR reading DCR 7 at startup! 'max retries' No watchpoint hardware found, HWP server not starting HWP server listening on host winxp (0.0.0.0), port 9928, address family IPv4 HWP server thread running! The simulation output shows me: # (minsoc_bench.minsoc_top_0.uart_top) UART INFO: Data bus width is 32. Debug Interface present. # # (minsoc_bench.minsoc_top_0.uart_top) UART INFO: Doesn't have baudrate output # # Running simulation: if you want to stop it, type ctrl+c and type in finish afterwards. # JTAG communication connected! Could it be, that there is something wrong with the IR-register length? I appreciate any hints and help, Christian

Sorry, but I don't know, where my newlines are gone ....

First, you should not have to specify the IR length, debug command, or target device index on the command line - there is a BSDL file included with the 'jtag' core that includes the first two, and the default index of 0 will work for this system. Just put this file in the search paths of adv_jtag_bridge, and it should work automatically.

Second, you should probably re-compile adv_jtag_bridge without JSP support. Unless you're using the JSP (and it looks like you're not), it will only slow things down.

Now, the real problem...errors from the HWP server reading the DCR registers are not fatal, but they suggest that there will be fatal errors later on when you actually try to do something useful. These errors usually indicate either a problem in the connection between the adv_dbg_if hardware and the OR1200, or a clocking or reset problem with the CPU. Check your simulation and make sure that the OR1200 is getting a clock signal, that it has been reset, and that the reset line is not active while the adv_dbg_if is trying to access the OR1200.

Thanks, that did it.

The clock-division setup was wrong.