Hello everyone,

the release candidate of MinSoC 1.0 is now over. A new board has been ported and some minor issues have been corrected. It is now mature for release. Below, I reintroduce 1.0's design idea and new features.

With version 1.0, we aim at facilitating the user and developer adoption of the system. MinSoC shall provide a framework for installation, configuration, simulation and synthesis. This way, changes to system internals and design can be made more easily, hopefully leveraging the development of MinSoC and OpenRISC.

There have been no changes to the RTL code. Of testbench and firmware, only few minor issues and warnings have been solved. As described above, the changes are in the framework.

These points summarize the newly implemented features:
-Installation and setup scripts: MinSoC required tools can be automatically installed and MinSoC can be automatically set up
-Unified project definition: define the project once, generate Icarus Verilog, ModelSim, ISE and Quartus projects
-Makefile system for synthesis: simply synthesize designs for Altera and Xilinx with "make all"
-board configuration: use a pre-built or port your board configuration.
-ModelSim simulation

Besides, MinSoC 1.0 works with fixed releases of the external cores. This way, the integration of these cores in MinSoC 1.0 is assured. UART, Ethernet and ADS are fixed to releases of the date of this post. *

In addition, we now support the watchpoint functionality of OpenRISC which has been worked out by the latest Advanced Debug System. For that, we apply ADS' patch for the debug interface of or1200 release 1 which also ensures the best debugging experience for now. Therefore, or1200 has been backported to release 1. *

Manuals for the usage of the release candidate can be found on our wiki under: http://www.minsoc.com/1_0:start

The system is simulatable out of the box. As soon as you take a pre-built board configuration, you can synthesize the design using the Makefile system.

Is your board not supported, it is easy to add the support. MinSoC still uses the traditional adaptation through minsoc_defines.v and creating the constraint file for pinout. Moreover, you can now specify the names for device and family part on a configure file to allow for synthesis using the Makefile system. More explanation about porting is available in the wiki under:
http://www.minsoc.com/1_0:board_configuration

You can still manually synthesize using your vendor workflow, on the wiki you find instructions on how to do so.

This release was only possible because of the good discussions the community provided on MinSoC usage, thanks for that. But the special thanks go for the new maintainers of MinSoC which provided some of the new ideas and the initial codes which finally achieved their goals.

I wish you a good time with MinSoC 1.0,
Raul Fajardo

* The MinSoC development branche (trunk) works with the up-to-date external cores. But a version release has to ensure correct integration for an unpredicted time. That does not allow for changes of external cores. Thus, we stick to the external core revisions of this date in MinSoC 1.0 which work in this setup.

Hi Raul,

Congratulations on the new release.

Jeremy

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Tel: +44 (1590) 610184
Cell: +44 (7970) 676050
SkypeID: jeremybennett
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Indeed. Great work Raul. Congratulations


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Olof Kindgren
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ORSoC
Website: www.orsoc.se
Email: olof.kindgren@orsoc.se
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FPGA, ASIC, DSP - embedded SoC design