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linting problem
by agathya on Dec 4, 2011
agathya
Posts: 2
Joined: Jul 27, 2011
Last seen: Mar 31, 2016
hello every body.. i have a code of 32 bit risc processor which is written in behavioral model.. when i tried to compile the code in rtl compiler by cadence i am getting many errors saying unsynthesizable constructs... now i am struck mid way of project, can anyone tell me the solution for thos.. can anyone converty the code in rtl compatible form..
plz do help me...
RE: linting problem
by agathya on Dec 4, 2011
agathya
Posts: 2
Joined: Jul 27, 2011
Last seen: Mar 31, 2016
hello every body.. i have a code of 32 bit risc processor which is written in behavioral model.. when i tried to compile the code in rtl compiler by cadence i am getting many errors saying unsynthesizable constructs... now i am struck mid way of project, can anyone tell me the solution for thos.. can anyone converty the code in rtl compatible form..
plz do help me...
RE: linting problem
by iztok on Dec 4, 2011
iztok
Posts: 7
Joined: Jul 9, 2008
Last seen: Apr 25, 2025
Hi,

Since you did not provide the language you use or a piece of source code, or the error message, we can only give you generic recommandations.

I assume you are not experienced enough to distinguish between constructs that can be synthesized and those that cant. Usually the first are a small subset of everything that can be simulated. This means that only a small part of all the code that can be written actually describes something that can be implemented with available hardware components.

I would suggest you start with a small piece of your project (adder, program counter) and try to compile, simulate, synthesize it separately from the rest of the project. At the same time try to immagine how this logic would look like constructed from combinatorial elements (and/or... gates, multiplexers, decoders) and sequential elements (registers, latches, counters, shift registers, memories).

In most cases the issue is that the synthesis tool can not translate the source into an appropriate sequential element. For example it is not possible to synthesize a register/memory with zero delay, such component requires a clock edge.

Regards,
Iztok Jeras
no use no use 1/1 no use no use
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