First let me say - thank you for the wonderful work on minsoc!!

I'm a newbie to opencores but have great interest in porting to the de2 wanted to ask if
any issues pop to mind in doing this, concerns, thoughts, warnings,...

Thanks,

Rich

What exactly are you trying to port? minsoc? custom openRISC setup?

MinSoc.

Thanks,

Rich

Thanks for the kind words Rich.

There should be no big deals when porting MinSoC to Altera DE2. All you have to know, should be written in our wiki. Please follow the guidance of the following link to proceed with your port:

http://www.minsoc.com/1_0:board_configuration#board_support

If you have any problems while doing so, post the specific problems and we look into it.

Regards,
Raul

Ok, it looks like I have the DE2_115 running with the JTAG UART wired in.

I'm wanting to bring up e-net next. I have two Marvell 88E111 Phys on the board. Any issues/guidance with bringing one of those online?

Thanks,

Rich

Hi Rich,

Simulate first:
-go to backend/minsoc_bench_defines.v and uncomment TEST_ETHERNET.
-go to sim/run generate_bench
-run_bench ../../sw/eth/eth.hex

The Ethernet firmware forwards back trough UART all data received from Ethernet on MinSoC. The testbench sends an Ethernet packet which is then output on the simulator screen. This can take around 10 minutes on simulation.

Once that works, you can repeat the same process on a serial terminal similar like gtkterm. To test Ethernet, you have to send an Ethernet packet to your board.

I have used the c source eth1_mac_snd.c found under minsoc/utils/contributions/eth_transf_linux. All you should have to do is:
-edit line 59 "eth1" to the Ethernet interface connected to your board
-compile the source gcc eth1_mac_snd -o ethsnd
-run the program with privileges (these kind of sockets (packet socket) require privileges)

You can also edit line 35 to match the MAC address of the Ethernet interface you are using to communicate with the board. I don't think this is necessary though.

Once the packet is sent, you should see the bytes received by the board on your serial terminal (e.g. gtkterm) the way you have seen them on simulation.

Of course, you have to connect the SoC first with the FPGA pins related to your PHY. I don't have the same PHY as you. You have to check board's user manual/datasheet to find out how to connect it. If your PHY does not have some of the required signals, you can connect these signals to FPGA pins left unconnected on the board. I have done so for spartan3e_starter_kit_eth:

45 NET "eth_trste" LOC = "p13"; #put it to a non connected FPGA pin (starter k it schematic BANK3)
46
47 NET "eth_fds_mdint" LOC = "r13" | PULLUP; #put it to a non connected FPGA pin (start er kit schematic BANK3)(pullup not to generate interrupts)

I think that's all. Good luck!

Raul

PS: I have seen some new board ports lately and that's awesome. It would be great if you guys can contribute with a backend directory related to your boards. This might imply that you have to leave out some features. In case that MinSoC really has to be adapted, I'm sure a maintainer would do it. I took the liberty of explaining under the following link how an extra board port should be committed to mainstream.

http://www.minsoc.com/1_0:board_configuration#testing_your_board_configuration