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minsoc + modelsim on 64 bit
by raghuraman on Jan 3, 2012
raghuraman
Posts: 7
Joined: Oct 13, 2010
Last seen: Dec 25, 2013
I ran into the following error when I try to simulate minsoc on modelsim on a 64 bit machine.

# vsim +file_name=../../sw/uart/uart.hex +firmware_size=7968 -lib minsoc -pli ../../bench/verilog/vpi/jp-io-vpi.so minsoc_bench
# Loading ../../bench/verilog/vpi/jp-io-vpi.so
# ** Error: (vsim-3197) Load of "../../bench/verilog/vpi/jp-io-vpi.so" failed: ../../bench/verilog/vpi/jp-io-vpi.so: wrong ELF class: ELFCLASS64.
# ** Error: (vsim-PLI-3002) Failed to load PLI object file "../../bench/verilog/vpi/jp-io-vpi.so".

What flags should I be adding in the Makefile to compile for 64 bit?

Also can someone share and how to on interfacing a xilinx ddr2 to minsoc. I have a XUPV5 board.

Thank you,
Raghu
RE: minsoc + modelsim on 64 bit
by rfajardo on Jan 3, 2012
rfajardo
Posts: 306
Joined: Jun 12, 2008
Last seen: Jan 6, 2020
Hi Raghu,

I ran into the following error when I try to simulate minsoc on modelsim on a 64 bit machine.

# vsim +file_name=../../sw/uart/uart.hex +firmware_size=7968 -lib minsoc -pli ../../bench/verilog/vpi/jp-io-vpi.so minsoc_bench
# Loading ../../bench/verilog/vpi/jp-io-vpi.so
# ** Error: (vsim-3197) Load of "../../bench/verilog/vpi/jp-io-vpi.so" failed: ../../bench/verilog/vpi/jp-io-vpi.so: wrong ELF class: ELFCLASS64.
# ** Error: (vsim-PLI-3002) Failed to load PLI object file "../../bench/verilog/vpi/jp-io-vpi.so".

What flags should I be adding in the Makefile to compile for 64 bit?


from what you described, it seems that your modelsim is 32-bit while your compiled vpi module 64-bit.

You could compile the vpi module with the -m32 flag. That should help. Or install a 64-bit version of modelsim.

-Change line 17 to:
16 jp-io-vpi.so: $(SRCDIR)jp-io-vpi.c Makefile
17 $(CC) -c -I$(MODEL)/modeltech/include $(SRCDIR)jp-io-vpi.c -o jp-io-vpi.o
18 $(CC) -shared -Bsymbolic -o jp-io-vpi.so jp-io-vpi.o -lc
to:
16 jp-io-vpi.so: $(SRCDIR)jp-io-vpi.c Makefile
17 $(CC) -m32 -fPIC -c -I$(MODEL)/include $(SRCDIR)jp-io-vpi.c -o jp-io-vpi.o
18 $(CC) -shared -Bsymbolic -o jp-io-vpi.so jp-io-vpi.o -lc

You might have already noticed that -fPIC is required.

-Recompile the library by issuing make.
-Copy jp-io-vpi.so to minsoc/bench/verilog/vpi.

You should be good to run.

Also can someone share and how to on interfacing a xilinx ddr2 to minsoc. I have a XUPV5 board.


I didn't try the DDR2 module. Other people can help you better in that regard. But XSoC (http://pm.stu.cn.ua/wiki/10/Getting_started) and orpsocv2 have implemented a Wishbone wrapper to the Xilinx MIG interface.

Raul
RE: minsoc + modelsim on 64 bit
by rfajardo on Jan 4, 2012
rfajardo
Posts: 306
Joined: Jun 12, 2008
Last seen: Jan 6, 2020
I forgot to mention that the Makefile, whose line 17 is to be changed can be found under:
minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/modelsim_linux_x86
RE: minsoc + modelsim on 64 bit
by raghuraman on Jan 4, 2012
raghuraman
Posts: 7
Joined: Oct 13, 2010
Last seen: Dec 25, 2013
Thank you Raul,

Works great now. Just one tiny mod, -m32 was also required for line 18.

16 jp-io-vpi.so: $(SRCDIR)jp-io-vpi.c Makefile
17 $(CC) -m32 -fPIC -c -I$(MODEL)/include $(SRCDIR)jp-io-vpi.c -o jp-io-vpi.o
18 $(CC) -m32 -shared -Bsymbolic -o jp-io-vpi.so jp-io-vpi.o -lc

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