About MinSoC port to Digilent Atlys board (Spartan 6).

From the last post here: http://opencores.org/forum,OpenRISC,0,4616

Hi Geoff,

Did you take care of adapting IN_CLK in board.h to be the input clock you are using divided by the number you set in minsoc_defines.v? If your IN_CLK is not set to the same as your board clock divided by the divisor in minsoc_defines.v, you will have this problems.

There are further possible problems, please check this:
http://www.minsoc.com/minsoc_faq#while_running_uart_firmware_example_on_my_fpga_the_data_shown_by_my_computer_s_terminal_are_weird_characters_instead_of_hello_world

By the way, I recommend to you that you simulate the same system taking care to adapt UART_BAUDRATE on minsoc_bench_defines.v. You should see the same weird characters there, in case your configuration is wrong somewhere.

Summarizing:
Board setup: board clock + minsoc_defines.v's divisor
Firmware setup: IN_CLK on board.h
Terminal setup: program dependent or UART_BAUDRATE on minsoc_bench_defines.v

All these setups must be consistent.

Best regards,
Raul

Hi Raul,

Thanks very much for the tips, I'll give those a try. I was getting a few other strange errors that made be a bit suspicious of the general stability of my port.

During my testing, my idea was to take the uart-to-USB chip on the Atlys board out of the loop and just connect the FPGA uart pins directly to the PMOD expansion port on the Atlys. However, just changing the pins in the .ucf file to connect to the PMOD caused some memory problems to pop up in the adv_jtag_bridge self test.

I'm hoping this is just a silly mistake on my part (I was also playing with the or1200 defines) so I'm backing out my changes now to try and put together a more methodical description of what I'm seeing. As I'm doing this, I'll try your suggestions to see if I can get a bit further.

Thanks,
Geoff