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Help needed on WISHBONE implementation
by niketh on Jan 31, 2012 |
niketh
Posts: 1 Joined: Jan 31, 2012 Last seen: Jul 17, 2012 |
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I am working on wishbone implementation in systemC language . I could find almost no past references to people who have worked on a similar topic . I would really appreciate if someone aware of it could assist me out . As i am working with systemC for first time , I am finding it difficult on following aspects --
- How to approach the implementation ? - How to realise higher abstraction ? - How to realise testbench and logging class ? Any sort of materials that can help me understand better will be very helpful . Thank you in advance Regards Niketh MG NITK surathkal |
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RE: Help needed on WISHBONE implementation
by rfajardo on Jan 31, 2012 |
rfajardo
Posts: 306 Joined: Jun 12, 2008 Last seen: Jan 6, 2020 |
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Hi Niketh,
- How to approach the implementation ?
You will probably want to create a transactor which translates transactions in signals. So you can execute things like write(addr,data) and the signals are generated for you. Read from TLM-1.0/docs/tlm_whitepaper.doc. If you want that your model is compatible, can be seamlessly used by others in other configurations, you can then port your implementation to TLM2.
- How to realise higher abstraction ?
I have written a very brief introduction on how/why to use SystemC and have a code example. I will attach this here. The text is in german. Use the online translator if needed. It seemed to do a decent job.
- How to realise testbench and logging class ?
Go through the example of systemc-2.2.0/docs/UserGuide20.pdf I hope that helps you somewhat. Raul
coprocessor_example.tar.bz2 (1155 kb)
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