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ERROR reading DCR 0 at startup! 'CRC mismatch' : altera NEEK:
by ravikiranyalamanchili on Feb 17, 2012 |
ravikiranyalamanchili
Posts: 3 Joined: Sep 20, 2011 Last seen: Feb 23, 2012 |
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Hi,
i am debugging a design which is similar to minsoc just that it has few additional applications on the ALtera NEEK.i am getting a CRC error when i run the adv_jtag_bridge, when i run the following line: sudo ./adv_jtag_bridge -l 0:10 ft245 'usb_blaster' interface using libftdi current latency timer: 2 Enumerating JTAG chain... Devices on JTAG chain: Index Name ID Code IR Length ---------------------------------------------------------------- 0: EP3C25F324 0x020F30DD 10 Target device 0, JTAG ID = 0x020f30dd IDCODE sanity test passed, chain OK! CRC ERROR! Computed 0x0, read CRC 0xffffffff Retry count exceeded! Abort! ERROR reading DCR 0 at startup! 'CRC mismatch' CRC ERROR! Computed 0x0, read CRC 0xffffffff Retry count exceeded! Abort! ERROR reading DCR 1 at startup! 'CRC mismatch' CRC ERROR! Computed 0x0, read CRC 0xffffffff Retry count exceeded! Abort! ERROR reading DCR 2 at startup! 'CRC mismatch' CRC ERROR! Computed 0x0, read CRC 0xffffffff Retry count exceeded! Abort! ERROR reading DCR 3 at startup! 'CRC mismatch' CRC ERROR! Computed 0x0, read CRC 0xffffffff Retry count exceeded! Abort! ERROR reading DCR 4 at startup! 'CRC mismatch' CRC ERROR! Computed 0x0, read CRC 0xffffffff Retry count exceeded! Abort! ERROR reading DCR 5 at startup! 'CRC mismatch' CRC ERROR! Computed 0x0, read CRC 0xffffffff Retry count exceeded! Abort! ERROR reading DCR 6 at startup! 'CRC mismatch' CRC ERROR! Computed 0x0, read CRC 0xffffffff Retry count exceeded! Abort! ERROR reading DCR 7 at startup! 'CRC mismatch' No watchpoint hardware found, HWP server not starting HWP server listening on host phlox.comira-east.lan (0.0.0.0), port 9928, address family IPv4 JTAG bridge ready! HWP server thread running! |
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RE: ERROR reading DCR 0 at startup! 'CRC mismatch' : altera NEEK:
by nyawn on Feb 21, 2012 |
nyawn
Posts: 173 Joined: Dec 19, 2008 Last seen: May 31, 2023 |
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The DCR failures are not necessarily fatal - the adv_jtag_bridge program automatically probes for watchpoint hardware at start-up. If the hardware is not there (and it will not be unless you are using the OR1200v1 and have applied my patch, distributed with the adv. debug sys), then adv_jtag_bridge will continue without it.
However, the fact that you are seeing CRC errors probably is fatal. Try running the self-test (use the -t option on the command line). I suspect it will fail, in which case you should see if your output matches something in the minsoc FAQ. If not, post the results here and I'll have a look. |
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RE: ERROR reading DCR 0 at startup! 'CRC mismatch' : altera NEEK:
by ravikiranyalamanchili on Feb 22, 2012 |
ravikiranyalamanchili
Posts: 3 Joined: Sep 20, 2011 Last seen: Feb 23, 2012 |
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hi,
here is what i get when i run the selftest: sudo ./adv_jtag_bridge -t ft245 'usb_blaster' interface using libftdi current latency timer: 2 Enumerating JTAG chain... Devices on JTAG chain: Index Name ID Code IR Length ---------------------------------------------------------------- 0: EP3C25F324 0x020F30DD 10 Target device 0, JTAG ID = 0x020f30dd IDCODE sanity test passed, chain OK! *** Doing self-test *** Stall or1k - CPU(s) stalled. SRAM test: ERROR! WB bus error during burst write, address 0xFFFFFFFF (index 0x3FFFFFFF), retrying! ERROR! WB bus error during burst write, address 0xFFFFFFFF (index 0x3FFFFFFF), retrying! ERROR! WB bus error during burst write, address 0xFFFFFFFF (index 0x3FFFFFFF), retrying! ERROR! WB bus error during burst write, address 0xFFFFFFFF (index 0x3FFFFFFF), retrying! ERROR! WB bus error during burst write, address 0xFFFFFFFF (index 0x3FFFFFFF), retrying! ERROR! WB bus error during burst write, address 0xFFFFFFFF (index 0x3FFFFFFF), retrying! ERROR! WB bus error during burst write, address 0xFFFFFFFF (index 0x3FFFFFFF), retrying! ERROR! WB bus error during burst write, address 0xFFFFFFFF (index 0x3FFFFFFF), retrying! ERROR! WB bus error during burst write, address 0xFFFFFFFF (index 0x3FFFFFFF), retrying! ERROR! WB bus error during burst write, address 0xFFFFFFFF (index 0x3FFFFFFF), retrying! ERROR! WB bus error during burst write, address 0xFFFFFFFF (index 0x3FFFFFFF), retrying! Max WB bus errors reached! or32_selftest.c:359: Jtag error 16 occured; exiting. |
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RE: ERROR reading DCR 0 at startup! 'CRC mismatch' : altera NEEK:
by nyawn on Feb 26, 2012 |
nyawn
Posts: 173 Joined: Dec 19, 2008 Last seen: May 31, 2023 |
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It looks like adv_jtag_bridge is talking to the cable and the hard TAP on the Altera chip, but may not be communicating with anything beyond that. Most probably, it's getting a '1' for every bit it reads. The most likely cause is a problem with the bitstream - either it was not downloaded to the FPGA correctly, or there is a problem with the reset line. Assuming you are using the altera_virtual_jtag TAP, there should not be a problem with the connections between the hard TAP, the soft TAP, and the debug core, but I'm not sure this has ever been tried on the FPGA you're using. Once you're sure your synthesized bitstream is good, and it's been downloaded, you may want to check the docs for that chip and make sure it supports the standard Altera "sld_virtual_jtag" core.
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