I tried changing the clmode_i values with no effect on the wishbone cycles. It looks like the logic that was once there hase been striped out and it now doesn't work.


This is a valuable feature to have and I am now working on a fix that will restore that function using an enabled clock signal for the cpu and seperate clock for everything else in the system. That lets you reduce the size of the high speed design and makes it easier to meet timing.

It will also remove the clmode_i pins and replaces them with a parameter.

John Eaton

Hi John,

Restoring this functionality seems like a good idea. As you say, it seems to have been removed for unknown reasons.

I'm a bit sceptic about using parameters for this though. Wouldn't this be good to have as a runtime option in case you want to do frequency scaling?

--
Olof Kindgren
______________________________________________
ORSoC
Website: www.orsoc.se
Email: olof.kindgren@orsoc.se
______________________________________________
FPGA, ASIC, DSP - embedded SoC design

I hadn't considered that feature. When a cpu is in a separate package than the rest of the system then it makes sense to use strapping pins to set the ratio so the board architect has control. But in an embedded system you will know beforehand what speed you can run everything so that you synthesis and time for those values.

I have done frequency switched designs for power savings and while they sound simple the design and verification effort is fairly massive. This is one of those things that will require a lot of effort and only benefit a very small number of users.

I am not going to sign up for that.

John Eaton

Hi All,
Not directly related to the clmode issue, but just out of interest, how many people who monitor these forums see no benefit from frequency scaling.
Put another way, who sees (low) power consumption as a major requirement in?
Steven

p.s. THis question in no way implies that John should put the effort in !

Power saving and frequency scaling is getting increasingly more important, and is something that we should look at more closely in the future.

But as John says, it's a complex topic, and would require much more work. If we want to have a scalable solution for power saving we would probably have to work on making all peripheral and CPU domains asynchronous to each other (Network On Chip seems to be the buzzword of the day for this). Restoring clmode won't be enough for a good low power infrastructure, but it is a nice feature, and will probably be useful in many cases anyway.

--
Olof Kindgren
______________________________________________
ORSoC
Website: www.orsoc.se
Email: olof.kindgren@orsoc.se
______________________________________________
FPGA, ASIC, DSP - embedded SoC design