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FPGA Debuggung trapped!
by Derek.Yu on Apr 28, 2012 |
Derek.Yu
Posts: 8 Joined: Apr 20, 2012 Last seen: Feb 18, 2013 |
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Hi all,
I have a FPGA development board with A3P1000 and a I/O board bought from: http://opencores.org/shop,item,1 http://opencores.org/shop,item,2 My development environment is Ubuntu VirtualBox image downloaded from: http://opencores.org/or1k/Ubuntu_VirtualBox-image_updates_and_information I can run my own C-program with or1ksim correctly, with debugging methods like step, set breakpoints, continue etc right. But when I try to debug my program on the FPGA board via or_debug_proxy and or32-elf-gdb, I got TRAP by breakpoints and never move on. If I run it free without breakpoints, everything is fine. If I set a break somewhere, it did stop, but will never leave that line even I delete the break. I am sure the program is compiled with -g and -O0 option. Is there any suggestion or solution for this debugging problem ? Thanks for any response. Best Regards, Derek |
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RE: FPGA Debuggung trapped!
by svenand on Apr 28, 2012 |
svenand
Posts: 31 Joined: May 12, 2009 Last seen: May 14, 2014 |
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I noticed the same thing when I was debugging the Atlys board.
http://www.rte.se/blog/blogg-modesty-corex/debugging-openrisc-1200 Sven |
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RE: FPGA Debuggung trapped!
by crevars on Apr 29, 2012 |
crevars
Posts: 29 Joined: Jun 7, 2008 Last seen: Mar 11, 2014 |
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I also had this problem and I'm working on it. Could you try to disable instruction cache ?
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RE: FPGA Debuggung trapped!
by Derek.Yu on May 3, 2012 |
Derek.Yu
Posts: 8 Joined: Apr 20, 2012 Last seen: Feb 18, 2013 |
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I have tried to disable the instruction cache under "ORSoC A3P1000 devboard" prompt by typing:
ORSoC A3P1000 devboard> ic_disable ORSoC A3P1000 devboard> dc_disable but it seems taking no effects on this problem. Is this disable thing takes effect for you? |
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RE: FPGA Debuggung trapped!
by crevars on May 3, 2012 |
crevars
Posts: 29 Joined: Jun 7, 2008 Last seen: Mar 11, 2014 |
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My problem was due to the sdram controller. I am using the soc from stefan (http://git.openrisc.net/cgit.cgi/stefan/orpsoc/) with the DE0 board.
The patches added on march (wb_sdram_ctrl/arbiter: connect coherency protection signals) fixed my problem. Which RTL are you using ? |
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RE: FPGA Debuggung trapped!
by Derek.Yu on May 4, 2012 |
Derek.Yu
Posts: 8 Joined: Apr 20, 2012 Last seen: Feb 18, 2013 |
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I'm not sure which version I use.
It comes with the A3P1000 FPGA (http://opencores.org/shop,item,1), and I have never changed it. So it might be the SOC design problem? |
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