Hello,

I am trying to get linux to start up on my de0-nano board. I have basically been following the tutorial at http://kevinmehall.net/openrisc/guide/ pretty closely, but now I have gotten to the end but it sort of starts up and then stops. (The same linux build works fine with the sim and xterm)

I am running Xubuntu under VirtualBox with Windows 7, but I don't actually think that's the issue, the device is programming fine and whatnot.

Anyway, when i load it up with adv_jtag_bridge and gdb I get the following and then the output just stops, and I get a CRC check error from the adv jtag bridge, as well as an error in the debugger:

*** Output from the uart port (pins on the bottom of the de0-nano board) ***
Compiled-in FDT at c0265820
Linux version 3.4.0-rc6-11570-gcc5234d-dirty (ibullock@ibullock-VirtualBox) (gcc version 4.5.1-or32-1.0rc1 (GCC) ) #3 Fri May 11 21:09:44 EDT 2012
CPU: OpenRISC-12 (revision 8) @50 MHz
-- dcache: 16384 bytes total, 16 bytes/line, 1 way(s)
-- icache: 16384 bytes total, 16 bytes/line, 1 way(s)
-- dmmu: 64 entries, 1 way(s)
-- immu: 64 entries, 1 way(s)
-- additional features:
-- debug unit
-- PIC
-- timer
setup_memory: Memory: 0x0-0x2000000
Reserved - 0x01ffda90-0x00002570
Setting up paging and PTEs.
map_ram: Memory: 0x0-0x2000000
On node 0 totalpages: 4096
free_area_init_node: node 0, pgdat c024c6f4, node_mem_map c03c4000
Normal zone: 16 pages used for memmap
Normal zone: 0 pages reserved
Normal zone: 4080 pages, LIFO batch:0
dtlb_miss_handler c0002000
itlb_miss_handler c0002108
OpenRISC Linux -- http://openrisc.net
pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768
pcpu-alloc: [0] 0
Built 1 zonelists in Zone order, mobility grouping off. Total pages: 4080
Kernel command line: console=uart,mmio,0x90000000,115200
Early serial console at MMIO 0x90000000 (options '115200')
bootconsole [uart0] enabled
PID hash table entries: 128 (order: -4, 512 bytes)
Dentry cache hash table entries: 4096 (order: 1, 16384 bytes)
Inode-cache hash table entries: 2048 (order: 0, 8192 bytes)
Memory: 28680k/32768k available (2055k kernel code, 4088k reserved, 301k data, 1416k init, 0k highmem)
mem_init_done ...........................................
NR_IRQS:32
100.00 BogoMIPS (lpj=500000)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 1024
devtmpfs: initialized
NET: Registered protocol family 16
Switching to clocksource openrisc_timer
NET: Registered protocol family 2
IP route cache hash table entries: 2048 (order: 0, 8192 bytes)
TCP established hash table entries: 1024 (order: 0, 8192 bytes)
TCP bind hash table entries: 1024 (order: -1, 4096 bytes)
TCP: Hash tables configured (established 1024 bind 1024)
TCP: reno registered
UDP hash table entries: 512 (order: 0, 8192 bytes)
UDP-Lite hash table entries: 512 (order: 0, 8192 bytes)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
Unpacking initramfs
Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
90000000.serial: ttyS0 at MMIO 0x90000000 (irq = 2) is a 16550A
console [ttyS0] enabled, bootconsole disabled
console [ttyS0] enabled, bootconsole disabled

***GDB LOG***
ibullock@ibullock-VirtualBox:~/linux$ or32-linux-gdb vmlinux --eval-command='target remote localhost:9999'
Building automata... done, num uncovered: 0/216.
Parsing operands data... done.
GNU gdb (GDB) 7.2-or32-1.0rc3
Copyright (C) 2010 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later " target="_blank">http://gnu.org/licenses/gpl.html>
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law. Type "show copying"
and "show warranty" for details.
This GDB was configured as "--host=i686-pc-linux-gnu --target=or32-linux".
For bug reporting instructions, please see:
..." target="_blank">http://www.gnu.org/software/gdb/bugs/>...
Reading symbols from /home/ibullock/linux/vmlinux...done.
Remote debugging using localhost:9999
0xfc384380 in ?? ()
(gdb) load
Loading section .text, size 0x201f40 lma 0x0
Loading section .rodata, size 0x1e210 lma 0x202000
Loading section __ksymtab, size 0x3c20 lma 0x220210
Loading section __ksymtab_gpl, size 0x1b90 lma 0x223e30
Loading section __ksymtab_strings, size 0xbb88 lma 0x2259c0
Loading section __param, size 0x1f0 lma 0x231548
Loading section .data, size 0x1b4a0 lma 0x232000
Loading section __ex_table, size 0x9f0 lma 0x24d4a0
Loading section .head.text, size 0x4000 lma 0x24e000
Loading section .init.text, size 0x116c8 lma 0x252000
Loading section .init.data, size 0x14b0ac lma 0x2636e0
Start address 0xc0000000, load size 3857532
Transfer rate: 15 KB/sec, 15874 bytes/write.
(gdb) jump *0x100
Continuing at 0x100.
Remote failure reply: E01

***adv_jtag_bridge output***

ibullock@ibullock-VirtualBox:~/adv_jtag_bridge$ sudo ./adv_jtag_bridge ft245
'usb_blaster' interface using libftdi
current latency timer: 2
Enumerating JTAG chain...

Devices on JTAG chain:
Index Name ID Code IR Length
----------------------------------------------------------------
0: EP4CE22F17 0x020F30DD 10

Target device 0, JTAG ID = 0x020f30dd
IDCODE sanity test passed, chain OK!
JSP server listening on host ibullock-VirtualBox (0.0.0.0), port 9944, address family IPv4
JSP server thread running!
No watchpoint hardware found, HWP server not starting
JTAG bridge ready!
CRC ERROR! Computed 0xfd802a2e, read CRC 0xc7d62aa
Retry count exceeded! Abort!

Error while reading all registers: 'CRC mismatch'


The errors (CRC mismatch and Remote Failure reply:E01) both occur right as it gets to the last bootconsole disabled messages.

Anyway, it seems like theres a ton of different versions or logs I could be providing so I'm not sure what would be most useful...

Oh, as a side note, I built all the tools with or32-linux rather than or32-elf, so I'm not exactly sure if that's okay or not...

Also, my device tree (dts) file is basically just the or1ksim.dts file with the 20Mhz speeds replaced with 50MHz for my device, so I'm not sure if I needed to adapt other things in that file as well...

Anyway, thanks for your input!

Cheers,
Ian

have a look here http://opencores.org/forum,OpenRISC,0,4807 ... try the patch provided by Nathan and see if it works for you ...

Thanks! Using the alternate OpenOCD connection helped. It still crashed in the same spot, but by looking at the simulator startup I was able to figure out that it was networking related - it turns out that I just needed to take the ethernet device out of my device tree and remove the ethernet support from the kernel, at which point it booted normally.

Are there any nice resources on using the GPIO drivers? I'd like to be able to access an 8-pin bank of GPIOs on my DE0-nano board, which is already set up in the hardware board build, but is absent from my device tree and the kernel config.

I still haven't found any great resources on how to do the device tree - I tried to add the GPIO based on some "aac.dts" I found, but I think some of the settings must be wrong because the kernel just crashes even in simulation.

Thanks,
Ian

I've copied the .dts file used for digilent altys port and modified it to suit my implementation. See attached.

Edit this and save this in your linux/arch/openrisc/boot/dts folder. then change to your linux dir and run 'make menuconfig'

Then browse to Processor Type & Features => Built-in DTB and type in the name of your dts file.

Hope this helps.

Regards,
AR

Here's the dts file ...

Hello,

I'm still facing the same problems while trying to run my system with linux+orpsoc+de0-nano:
I caught the same output than ibullock:

---- adv_jtag_bridge output ----- :
...
CRC ERROR! Computed 0x8286c7a2, read CRC 0xadc18357
Retry count exceeded! Abort!

Error while reading all registers: 'CRC mismatch'
...

----- gdb output ------ :
...
Start address 0xc0000000, load size 2831374
Transfer rate: 46 KB/sec, 15642 bytes/write.
(gdb) jump *0x100
Continuing at 0x100.
Remote failure reply: E01


However, my simulation works well on or1ksim.
The network driver is disabled from both the kernel and .dts file.
The simulation output shows icache and dcache disabled. I didn't find how to enable it on last linux kernel version provided by 'git://git.openrisc.net/jonas/linux'

I can't find the OpenOCD patch files provided by Nathan. The .tgz I found here: http://openrisc.2316802.n4.nabble.com/attachment/4535966/0/patch_adv_debug_sys.tar.gz has a corrupted file.

Could someone aid me?
Thanks

Hi,

The OpenOCD patched to use adv_debug_sys can be found here: http://git.openrisc.net/cgit.cgi/julius/openocd/log/?h=adv_debug_sys

./configure --enable-usb_blaster_libftdi --enable-adv_debug_sys
--enable-maintainer-mode

And this is the startup script tu use:

source [find ./tcl/interface/altera-usb-blaster.cfg]
usb_blaster pin6 1
usb_blaster pin8 1
source [find ./tcl/target/vjtag.cfg]

proc fpga_test_init {} {


}

gdb_port 50001

init
#echo "Halting processor"
halt

foreach name [target names] {
set y [$name cget -endian]
set z [$name cget -type]
puts [format "Chip is %s, Endian: %s, type: %s" \
$name $y $z]
}

You'll also have to put your FPGA JTAG ID in vjtag.cfg.

Franck.

Yeah, make sure you disable ethernet both in the device tree and also disable the networking support in menuconfig. I'm not sure why this latter step was necessary, but in my case it allowed linux to finish booting successfully.

In general I'd recommend looking at the output from your device terminal and comparing it to the simulator to try to see which stage of the startup it is crashing at - that's what helped me to narrow it down to the network setup in my case.

Has anyone gotten SD card support working with the de0-nano board yet? I tried adding it to the board config but there seem to be some complilation errors, maybe relating to reset configuration or some such. it seems like the version of the sd card controller for the new dev board should be suitable for altera synthesis but I'm having trouble finding it without downloading the whole virtualbox image. Maybe someone could point me to the right part of whatever repository?

Thanks!

Hi,
Thanks for the answers.

I'm using openocd as crevars metioned
I have .cfg files with the content as suggested by crevars.

This is my output from openocd :

$openocd -f tcl/openocd/openocd.cfg
Open On-Chip Debugger 0.5.0-dev-gd469a0b (2012-05-22-15:06)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.berlios.de/doc/doxygen/bugs.html
Warn : Adapter driver 'usb_blaster' did not declare which transports it allows; assuming legacy JTAG-only
Info : only one transport option; autoselect 'jtag'
3000 kHz
Info : No lowlevel driver configured, will try them all
Info : usb blaster interface using libftdi
Error: Translation from khz to jtag_speed not implemented
Error: Translation from khz to jtag_speed not implemented
Error: Translation from jtag_speed to khz not implemented
Info : adapter-specific clock speed value -554478528
Info : JTAG tap: or1k.cpu tap/device found: 0x020f30dd (mfg: 0x06e, part: 0x20f3, ver: 0x0)
Warn : JTAG tap: or1k.cpu UNEXPECTED: 0x020f30dd (mfg: 0x06e, part: 0x20f3, ver: 0x0)
Error: JTAG tap: or1k.cpu expected 1 of 1: 0x020b30dd (mfg: 0x06e, part: 0x20b3, ver: 0x0)
Error: Trying to use configured scan chain anyway...
Warn : Bypassing JTAG setup events due to errors
target state: halted
Chip is or1k.cpu, Endian: big, type: or1k
Info : accepting 'gdb' connection from 50001
Warn : acknowledgment received, but no packet pending

Is there a de-nano.cfg or something else?
or1k.cpu is not apparently the right file.
The vjtag.cfg is matching my FPGA's JTAG ID, but I dont know what to do with the error messages.

The GDB output seems ok:
(gdb) load
Loading section .text, size 0x12317c lma 0x0
Loading section .rodata, size 0x11d88 lma 0x124000
Loading section __ksymtab, size 0x2810 lma 0x135d88
Loading section __ksymtab_gpl, size 0x1068 lma 0x138598
Loading section __ksymtab_strings, size 0x77b6 lma 0x139600
Loading section __param, size 0xd0 lma 0x140db8
Loading section .data, size 0x16240 lma 0x142000
Loading section __ex_table, size 0x7e0 lma 0x158240
Loading section .head.text, size 0x4000 lma 0x15a000
Loading section .init.text, size 0xdcd0 lma 0x15e000
Loading section .init.data, size 0x14ad1c lma 0x16bce0
Start address 0xc0000000, load size 2831374
Transfer rate: 22 KB/sec, 15642 bytes/write.
(gdb) jump *0x100
Continuing at 0x100.

I can download linux through gdb, but I can't see the serial terminal output.

Hmm, it's possible there are still some config issues. I don't have my virtual machine open right now but according to my notes i used a command something like:

sudo ./src/openocd -f ./tcl/interface/altera-usb-blastecfg -f altera-dev.tcl

I think there might be some characters missing there from when i copy and pasted, not sure.

But yeah, I pretty much just followed the stuff at:
http://opencores.org/forum,OpenRISC,0,4807

Double check that you're reading from the right serial pins on the board, and that your baud rate is set right on your serial device (115200 i believe)! :)

If you email me at bullock.ian@gmail.com and let me know what files you want (config files, etc), I can try to email you back my versions, or maybe even a prebuilt board image to test with...

Hi,

I don't know if I have to consider these openocd error messages even if gdb output seems ok:
...
Info : JTAG tap: or1k.cpu tap/device found: 0x020f30dd (mfg: 0x06e, part: 0x20f3, ver: 0x0)
Warn : JTAG tap: or1k.cpu UNEXPECTED: 0x020f30dd (mfg: 0x06e, part: 0x20f3, ver: 0x0)
Error: JTAG tap: or1k.cpu expected 1 of 1: 0x020b30dd (mfg: 0x06e, part: 0x20b3, ver: 0x0)
Error: Trying to use configured scan chain anyway...
...

Here are my openocd scripts:

--- altera-usb-blaster.cfg ---

interface usb_blaster
adapter_khz 3000
-----------------------------


--------- vjtag.cfg ---------
set _CHIPNAME or1k
set _ENDIAN big

# force an error till we get a good number
# Your FPGA JTAG ID
set _FPGATAPID 0x020B30DD

# jtag scan chain
# format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
# All altera FPGA have IRLEN = 10
jtag newtap $_CHIPNAME cpu -irlen 10 -expected-id $_FPGATAPID

set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
target create $_TARGETNAME or1k -endian $_ENDIAN -chain-position $_TARGETNAME
-----------------

altera-dev.cfg is the same as motioned above by 'crevars'.



Another issue is the serial communication. I have a cable from my PC(serial port) where some wires(Rx, Tx, GND) are connected directly on GPIO pins of DE0-Nano board. My question is: I need a converter like maxi232 in this case to convert from PC voltage levels into DE0-Nano?

Thanks.

Hi,

Info : JTAG tap: or1k.cpu tap/device found: 0x020f30dd (mfg: 0x06e, part: 0x20f3, ver: 0x0)
Warn : JTAG tap: or1k.cpu UNEXPECTED: 0x020f30dd (mfg: 0x06e, part: 0x20f3, ver: 0x0)

--> It seems you're using a EP3C25 device.

# force an error till we get a good number
# Your FPGA JTAG ID
set _FPGATAPID 0x020B30DD

--> This is the JTAG ID of the fpga I'm using (Cyclone II). You have to change this value with ++your++ JTAG ID.

However, it's not a big deal as it works anyway....

To answer your second question: yes, you need to convert the signals from RS232 to TTL.

Franck.

Hello Frank,
thanks for the help

I'm using a DE0-Nano board with a Cyclone IV

This is the output from jtagconfig:
1) USB-Blaster [2-1.3]
020F30DD EP3C25/EP4CE22

What's the correct ID ?

because of it I use 020F30DD as _FPGATAPID

sorry Frank,

It worked now with the correct ID from jtagconfig.

I didn't realize that they were almost the same:
(0x020B30DD) and (0x020F30DD).

Once again, Thanks for the help.