I have integrated the latest version of ADI module (adv_dbg_if) with the latest version of OR1200. When I configure OR1200 to 1:2 WB to CPU Clock using CLMODE strap bits, some commands to the ADI module are failing. I observed that it doesn't take CLMODE strap bits amd also doesn't have synchronization logic between WB and CPU interface, probably assuming same clock.
Please let me know if anybody has fixed this issue.

Thanks,
Rajani

No part of the ADI assumes that it is at the same clock as anything else. The WishBone interface and the OR1200 are each synchronized (using dual latching and toggle signalling) to the JTAG clock domain. There is no synchronization between the OR1200 and the Wishbone because none is necessary. The WishBone interface of the ADI has an input for the WishBone clock. The OR1200 interface of the ADI has an input for the CPU clock.

The OR1200 clock input to the ADI must be the same speed as the internal clock of the OR1200. So, if the OR1200 is dividing it by two before using it, then you need to also divide the CPU clock to the ADI by two.

I am giving the same CPU Clock to ADI CPU_CLK input and OR1200_CPU_CLK input.
The CPU clock is twice the frequency of WB clock.

I am seeing a failure for STALL/RESET instruction from ADI write, where the WB STB and CYC are de-asserted before ACK is received from the WB slave.

I am attaching a snapshot of wave dump, please let us know if you need any further information to debug this issue.
Please check out at instance 67574ns.

Thanks,
Rajani

Your terminology confused me. The ADI wishbone interface does not have a STALL instruction, that is only used with the CPU module. The RESET instruction is handled at the JTAG TAP level, it is neither a CPU nor a Wishbone command in the ADI.

I looked at your waveform. The short answer is that your JTAG clock (TCK) is far too fast for your CPU and WishBone clock. You are transferring another entire 32 bit word to the ADI WishBone interface before it can finish sending the first word over the WishBone. Unless you are using 'legacy mode' (which waits for the WishBone bus to be ready, and is very slow), this will cause errors.

If you are transferring to a WishBone target with a one-clock write cycle, then the ADI needs ~4 WishBone clock cycles to do a transaction. During this time, no more than ~9 TCK cycles should occur (to insure that a burst of 8-bit word writes succeed). Your waveform shows about 1.5 CPU clock cycles, and more than 32 TCK cycles. Slow down your TCK, or speed up your WishBone (and CPU) clock.

Thanks for your help, when I reduced the TCK to be ~1MHz for a 12.5MHz WB clock, the issue doesn't occur.

-Rajani