Hello,

We are seeing some timing violations in the Debug Unit (DU) of OR1200, and all the paths are through "du_hwbkpt" (hardware breakpoint) logic. Please let me know if these paths can be considered multi-cycle paths (the sdc in svn doesn't have any such false/multicycle paths defined though).
Logically thinking, the hardware breakpoint may take few cycles to be realised by all parts of the CPU (pipeline stages, bus interfaces etc).

Thanks,
Rajani

hi, can you elaborate what kind of difficulties yor are experiencing, since am too working on the functionality of OR1200 ISA.

we might be able to help each other.

Thanks Hemanth for your help.

We were making trials on OR1200 to see upto what frequency we can take the CPU to and when I included DU_HWBKPT logic (using or1200_defines.v and without MAC and FPU), we were seeing violations through the "du_hwbkpt" signal (~800). When I omit the logic by commenting the define in or1200_defines.v, the pre-synthesis timing was good.
Looking at the logic, we were not sure if these paths were supposed to be multi-cycle and hence the question.

Please let me know if you have gone through these paths before. Let me know if you need further information.

Thanks,
Rajani

hi, I still do not have a clear idea about what you are experiencing. But I am saying what i know about the du_hwbkpt signal. It triggers the exception, running for three cycles just like a trap exception. Hope it helps.