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Running single test of or1ksim
by vjraj on Jul 9, 2012 |
vjraj
Posts: 30 Joined: Jun 2, 2010 Last seen: Jan 15, 2017 |
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Hi All,
I had run the or1ksim test suite and it worked fine after configuring/installing etc. But now I am trying to run a single test to understand the execution better. I am giving the following command for running the "basic" test: or32-elf-sim -iVt testsuite/test-code-or1k/basic/basic The test is giving out the following output and doesn't stop: Verbose on, simdebug off, interactive prompt on Machine initialization... Clock cycle: 4ns No data cache. No instruction cache. BPB simulation off. BTIC simulation off. Or1ksim 0.5.0rc2 Building automata... done, num uncovered: 0/213. Parsing operands data... done. Resetting Tick Timer. Resetting Power Management. Resetting PIC. Starting at 0x00000000 loadcode: filename testsuite/test-code-or1k/basic/basic startaddr=00000000 virtphy_transl=00000000 Not COFF file format ELF type: 0x0002 ELF machine: 0x005c ELF version: 0x00000001 ELF sec = 6 Section: .text, vaddr: 0xf0000000, paddr: 0xf0000000 offset: 0x00002000, size: 0x000006dc ERR: 8-bit program load out of memory area: f0000000 ERR: 8-bit program load out of memory area: f0000001 ERR: 8-bit program load out of memory area: f0000002 ERR: 8-bit program load out of memory area: f0000003 ERR: 8-bit program load out of memory area: f0000004 ERR: 8-bit program load out of memory area: f0000005 ERR: 8-bit program load out of memory area: f0000006 ERR: 8-bit program load out of memory area: f0000007 ERR: 8-bit program load out of memory area: f0000008 I am also attaching a file with this output, please go through it. Please let me know if I am missing out anything in running a single test. Also, please let me know how to enter into CLI mode. Regards, Rajani
tmp (103 kb)
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RE: Running single test of or1ksim
by olof on Jul 9, 2012 |
olof
Posts: 218 Joined: Feb 10, 2010 Last seen: Dec 17, 2018 |
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You might need to supply a configuration file. Add -f </path/to/or1ksim.cfg>
-- Olof Kindgren ______________________________________________ ORSoC Website: www.orsoc.se Email: olof.kindgren@orsoc.se ______________________________________________ FPGA, ASIC, DSP - embedded SoC design |
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RE: Running single test of or1ksim
by vjraj on Jul 11, 2012 |
vjraj
Posts: 30 Joined: Jun 2, 2010 Last seen: Jan 15, 2017 |
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Thanks Olof, I could enter the CLI by adding the cfg file. But when I dump the memory from 0x100 (boot address), it is showing all 0s. Plese let me know what could be the issue, first of all whether the testcase object file is loaded into some memory or not.
Thanks, Rajani |
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RE: Running single test of or1ksim
by vjraj on Jul 13, 2012 |
vjraj
Posts: 30 Joined: Jun 2, 2010 Last seen: Jan 15, 2017 |
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After running the command with "cfg" file, I am observing that the simulator doesn't go forward beyond 0x100 and 0x104 locations. And these locations are showing zeroes in the dump. Please let me know if I am missing something else.
Thanks, Rajani or32-elf-sim -iVt testsuite/test-code-or1k/basic -f ../or1ksim_be/sim.cfg Reading script file from "./../or1ksim_be/sim.cfg"... Warning: ./../or1ksim_be/sim.cfg: Unrecognized parameter: section at line 467; ignored. Verbose on, simdebug off, interactive prompt on Machine initialization... Clock cycle: 100ns No data cache. No instruction cache. BPB simulation off. BTIC simulation off. Or1ksim 0.5.0rc2 Building automata... done, num uncovered: 0/213. Parsing operands data... done. Warning: PS2 keyboard unable to open RX file stream. Resetting Tick Timer. Resetting Power Management. Resetting PIC. Starting at 0x00000000 loadcode: filename testsuite/test-code-or1k/basic startaddr=00000000 virtphy_transl=00000000 identifyfile2: Is a directory 00000100: 00000000 l.j 0x0 (executed) [cycle 0, #1] 00000104: 00000000 l.j 0x0 (next insn) (delay insn) GPR00: 00000000 GPR01: 00000000 GPR02: 00000000 GPR03: 00000000 GPR04: 00000000 GPR05: 00000000 GPR06: 00000000 GPR07: 00000000 GPR08: 00000000 GPR09: 00000000 GPR10: 00000000 GPR11: 00000000 GPR12: 00000000 GPR13: 00000000 GPR14: 00000000 GPR15: 00000000 GPR16: 00000000 GPR17: 00000000 GPR18: 00000000 GPR19: 00000000 GPR20: 00000000 GPR21: 00000000 GPR22: 00000000 GPR23: 00000000 GPR24: 00000000 GPR25: 00000000 GPR26: 00000000 GPR27: 00000000 GPR28: 00000000 GPR29: 00000000 GPR30: 00000000 GPR31: 00000000 flag: 0 (sim) t 00000104: 00000000 l.j 0x0 (executed) [cycle 1, #2] 00000100: 00000000 l.j 0x0 (next insn) (delay insn) GPR00: 00000000 GPR01: 00000000 GPR02: 00000000 GPR03: 00000000 GPR04: 00000000 GPR05: 00000000 GPR06: 00000000 GPR07: 00000000 GPR08: 00000000 GPR09: 00000000 GPR10: 00000000 GPR11: 00000000 GPR12: 00000000 GPR13: 00000000 GPR14: 00000000 GPR15: 00000000 GPR16: 00000000 GPR17: 00000000 GPR18: 00000000 GPR19: 00000000 GPR20: 00000000 GPR21: 00000000 GPR22: 00000000 GPR23: 00000000 GPR24: 00000000 GPR25: 00000000 GPR26: 00000000 GPR27: 00000000 GPR28: 00000000 GPR29: 00000000 GPR30: 00000000 GPR31: 00000000 flag: 0 00000104: 00000000 l.j 0x0 (executed) [cycle 2, #2] 00000100: 00000000 l.j 0x0 (next insn) (delay insn) GPR00: 00000000 GPR01: 00000000 GPR02: 00000000 GPR03: 00000000 GPR04: 00000000 GPR05: 00000000 GPR06: 00000000 GPR07: 00000000 GPR08: 00000000 GPR09: 00000000 GPR10: 00000000 GPR11: 00000000 GPR12: 00000000 GPR13: 00000000 GPR14: 00000000 GPR15: 00000000 GPR16: 00000000 GPR17: 00000000 GPR18: 00000000 GPR19: 00000000 GPR20: 00000000 GPR21: 00000000 GPR22: 00000000 GPR23: 00000000 GPR24: 00000000 GPR25: 00000000 GPR26: 00000000 GPR27: 00000000 GPR28: 00000000 GPR29: 00000000 GPR30: 00000000 GPR31: 00000000 flag: 0 (sim) |
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