Hi, does any one know how many cycles it takes for a load/store instruction to perform its operation in all the possible cases such as a cache hit and cache miss?

That depends on the memory type, the memory controller and the OpenRISC implementation
(it's not guaranteed anywhere in the spec that an addition for example _has_ to be
a 1-cycle operation, so of course load/stores are valid to vary as much as they like too).
If you want some worst-case for a given setup, that's possible to get,
but then we would need to know what kind of setup you have.

hi stekern, thanks for the reply

hi, I am looking at the implementation of OR1200 processor and found some things I could not understand. I hope that you guys can help me with this..
1) Why is an if_stall(comes from if stage, if.v) used in freeze signals(freeze.v)? since this says that if there is no insn in the if stage, all the stages in the pipeline can be frozen, which I think may not be a correct way for implementing a pipeline.
2) Why is id_freeze not asserted high when there is a data error or an illegal insn is recognized eventhough ex_freeze and wb_freeze are asserted high? Because, this would cause the id stage to process the insn and are lost until ex_freeze gets asserted to low again.

In the case of the OR1200, this is practically equivalent to not freezing later stages, but inserting bubbles.



Interrupts and exceptions are processed in the execute stage, the last stage before ISA-level state gets updated by an instruction. The act of processing an interrupt or exception in the EX stage will cause all processing done in the ID and IF stages to be flushed as control passes to the handler.

hi firefalcon, thank you for the reply, this cleared many of my assumptions about the design..

will it be efficient if we introduce cyclic passing of a stall signal to each phase(if necessary add some additional signals for the later stages)?? Because then it would not effect the insns that are in the later pipeline stages.

More efficient as in less power, higher throughput? Is the goal to allow instructions in later pipeline stages to advance even if previous pipeline stages are stalled? For many reasons, this approach would provide a small throughput advantage at the cost of increased power usage.