Hi,

I want to program the OpenRISC processor on an Altera FPGA. I have replaced all internal memories with Alter FPGAs and they work properly. But external memory (located in ram_wb_b3.v file) has a behavioral description. How can I use a memory instead of this description?

Behavioral memories should be translated to real ones by the synthesizer. However, that may not always work.

Here is what I used a while back when I did a project with openrisc

https://github.com/Deathbobomega/thermostat/blob/master/src/wb_memory/wb_RAM.sv
https://github.com/Deathbobomega/thermostat/blob/master/src/wb_memory/InferableRAM.sv

You will have to port the wb_RAM as I highly doubt it will work out of the box since I was using my own custom interfaces for the wishbone bus.

Both minsoc and orpsocv2 projects can be synthesized to Altera FPGAs.

If you only want to connect FPGA memory to the Wishbone bus, you can use these two files:
http://opencores.org/websvn,filedetails?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Frtl%2Fverilog%2Fminsoc_onchip_ram_top.v
http://opencores.org/websvn,filedetails?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Frtl%2Fverilog%2Fminsoc_onchip_ram.v

Raul

It seems that links are broken

try this:
http://opencores.org/websvn,filedetails?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2Fverilog%2Fram_wb%2Fram_wb.v

works for altera cyclone IV

This one is synthesizable, but the ram_wb_b3 is not.

I remember that I could synthesize it for cyclone IV in quartus 11.0, but I'll check it again later today.

In fact, I didn't have to change anything in the orpsocv2 to synthesize successfully.
You can check my fork:
https://github.com/mczerski/orpsoc-de0_nano