Hi Kuoping,

Please let me know if the patch expects the testcode to be in Little Endian format. I have added your patch to my latest RTL and I have a testcase that is apparently in little endian format, but the CPU is not able to understand the code. I think the patch doesn't include logic to pick up the instructions in a different order if the code is also little endian.
Please let me know.

Thanks,
Rajani


by Kuoping on May 18, 2012

Quote

Kuoping
Posts: 27
Joined: Mar 27, 2009
Last seen: Aug 24, 2012

This is my patch for the little-endian support on RTL code.

http://opencores.org/forum,OpenRISC,0,4093

But there's no toolchains to support it yet.

hi vjraj,

The little endian patch only effect the load/store unit. The wishbone interface must swap the byte order depends on the endian type.

If you program the processor as little endian, the wishbone interface dose not swap the byte order. In such condition, the text code and date are both little endian when they store in the memory.

The patch doesn't include logic to pick up the instructions in a different order if the code is also little endian, you do not need swap the byte order in the instruction wishbone interface. The orpsocv2 is for big endian only, it dose byte swap in somewhere. It will cause incorrect execution, if you use the little endian text code. So you need modify the code, I think the code is on the ram_wb_b3.v.

Kuoping

How about IMMU?? I guess the tables are still in BE order, and hence if we want to load the TLBs statically, they would have to be written in BE order. Please comment.

Thanks,
Rajani