HI,
I have used ORPSOCv2 to get a .vmem file (in linux). Now I would like to use Modelsim in window machine to read the .vmem and get the result. I have copied the whole folder orpsocv2/rtl/verilog into my windows machine. All the verilog files are in one folder. Then I use modelsim to compile the files. After that, I got errors from the orpsoc-params.v , like:
: (vlog-2730) Undefined variable: 'rom0_wb_adr'.
: 'rom0_wb_adr' already declared in this scope (work).

I have try to delete the orpsoc files but it still doesnt work. Since I am no longer using ORPSOC, so that should not be included in the modelsim project?right?

What files should I include in the project then? everything seems like linking together..

Thank you very much for the help
Dan

Also I have tried to use modelsim in linux. I changed the simulator in sim/bin/Makefile to
SIMULATOR ?=$(Modelsim), then I type: make rtl-test USER_VEME=/home/openrisc/soc-design/orpsocv2/testing/test1.vmem VCD=1
The simulation wave in modelsim doesnt come out

Hi,

You should not include orpsoc-params.v in your modelsim project. However, this file (and orther files "included") should be in an include directory specified in Modelsim.

You can select all your project verilog files then right clic -> properties -> verilog & SystemVerilog -> Include Directory.

Franck.

Thank you for your reply Franck

How about he bootrom.v file?Its just:
0 : wb_dat_o 1 : wb_dat_o 2 : wb_dat_o ...
..
.

It doesnt include any "module heading". Like "module FSM(.....)" and "always@". It cannot pass the compile in the modelsim, so do I need to change it to be "always@"?

You also have to include the path to bootrom.v in properties of rom.v. As you can see in rom.v, the bootrom.v file is included as is.

Thank you very much
But sorry for one more question,when I check the icarus.scr file in sim/run (which shows the simulation files used) it used the bench/verilog file for testbench. In the bench folder, it has usbhostslave, vpi and some monitor files. Since I am not gonna input my result into FPGA. So the usbhostslave and vpi files are not required to use in my modelsim simulation. So wt I need for the testbench are just the verilog file in bench/verilog and bench/verilog/include, but not bench/verilog/usbhostslave and bench/verilog/vpi. Is that right?

Dan

What you need to run the testbench is files for modules instantiated in the bench.

In your bench you'll have orpsoc_top as device under test and models of your hardware component connected to the DUT.

So if you orpsoc uses SDRAM, you need to connect an SDRAM model to the SDRAM port of orpsoc in the testbench.

I'm not sure I answered your question...

Franck.

Thanks, I am now clear how it works