Hi,
To run the OR1200 in non-nested exception mode, disabling the SR[CE] bit is enough or do we need to disable all the exceptions in the ISR. Somewhere in the documentation it is mentioned that every exception sets new SR with timer and ext interrupt disabled bits. I came across a problem like where EPCR is over written by nested exception ended up in bus error. SR[CE] bit is disabled in this case and timer exception is disabled and again enabled.

Thanks,
A.Vamsi

i need "sys/alt_irq.h" header file for my project please send me

i am working on cycloneII board , i need "sys/alt_irq.h" header file for nios II.

Hi,

As far as I know, this is an OpenRISC forum....

Franck.

Hi Franck,

Could you please tell me where to post OR1200 related stuff on opencores forum. As for as I know, OpenRISC 1200 is an implementation of OpenRISC 1000 processor family.

Thanks,
A.vamsi

You can disable interrupts, but not exceptions. There is a lot of confusion in your question. You should re-read the architecture specification, especially how exceptions work and the SR and exception registers.

Some things to think about:
SR[IEE]
SR[TEE]
exception vs. interrupt
resumable vs non-resumable exception/interrupt
How PC, SR, ESR, ECPR, and EEAR are updated when an exception/interrupt occurs
How PC, SR, ESR, ECPR, and EEAR are updated when an l.RFE is processed

Sorry avamsi, it was a comment for nages post, asking for nios2 files....

Franck.

hi firefalcon,

I re-looked into the documents. Actually this is the case where I want to check the execution.
Case1:: Initially I enabled the SR[TEE] and SR[IEE] bits and SR[CE] is disabled. Now timer interrupt has come, current PC and SR are saved in the EPCR0 and ESR0 registers.Now PC is loaded with 0x500 and SR is loaded with the following bits from the below explanation.

"All exceptions set a new SR where both MMUs are disabled (address translation
disabled), supervisor mode is turned on, and tick timer exceptions and interrupts are
disabled. (SR[DME]=0, SR[IME]=0, SR[SM]=1, SR[IEE]=0 and SR[TEE]=0)."

Now when executing in the timer ISR, I guess the external interrupt is ignored, and when it returns from ISR, PC and SR are restored with EPCR0 and ESR0 values . Here after external interrupts are served.

Case2:: Initially I set the SR[TEE] and SR[IEE] bits and SR[CE] is not set. Now external interrupt has come, current PC and SR are saved in the EPCR0 and ESR0 registers.Now PC is loaded with 0x800 and SR is loaded with the following bits(SR[DME]=0, SR[IME]=0, SR[SM]=1, SR[IEE]=0 and SR[TEE]=0).Now when executing in the ext interrupt ISR, I guess the timer interrupt is ignored, and when it returns from ISR, PC and SR are restored with EPCR0 and ESR0 value. Hereafter timer interrupts are served.
With this understanding if I execute the code it is halting in the middle after some iterations.It seems still the interrupts are troubling each other. Otherwise do I have to diable the SR[TEE] and SR[IEE] explicitly in the ISR execution.

i need i2c master vhdl code ,i am working in cyclone board, please send me code

First, you can safely ignore SR[CE] as the OR1200 does not support it. Second, you should know that the OR1200 is far from a correctly functioning processor, especially some of the exception handling logic---I learned this the hard way. Your problem, like many that I experienced, could be due to a hardware bug. One thing to check is if the interrupts/exceptions are firing within a few clock cycles of each other. This causes the processor to lock. I forget all the details, and still need to submit my patches.

Without a very detailed trace of what is going on, it will be hard for me to be more helpful.

hi firefalcon,
When I examined the SR reg value after entering the ISR of timer or external interrupt, it holds the values SR[DME]=0, SR[IME]=0, SR[SM]=1, SR[IEE]=0 and SR[TEE]=0. Now it is sure that it is supposed to ignore any other timer or external interrupts in it's ISR. But during execution, after some iterations it hangs.And the point where it hangs is always not same. Currently I am working on the RTL available on openrisc svn.