Hi.
When MMU is on in OpenRisc 1200 IP Core Spec(http://www.openrisc.net/or1200-spec.html)
Cached and uncached regions is defined like the below.
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Table 3.6 Cached and uncached regions
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Effective Address Region
0x00000000 - 0x3FFFFFFF Cached
0x40000000 - 0x7FFFFFFF Uncached
0x80000000 - 0xBFFFFFFF Cached
0xC0000000 - 0xFFFFFFFF Uncached
And spec refers to the following.
Caching-inhibited(CI) attribute is not implemented in OR1200 DTLB.

However, linux's kernel'start address is 0xc0000_0000 and device driver address start at 0xbc00_0000.
According to Table 3.6 in Spec.
0xC000_0000 is in Uncached region and 0xbc00_0000 is in 0xbc00_0000 in cached region.
This make no sence.

Cached and Uncaned regions are fixed ?
Or, Can I separate these regions ?

Thanks,
BestHwang

The uncached regions are based-on physical addresses. The kernel address you are seeing is a virtual address. Unless you have a gigabyte of RAM, the kernel is being cached.

Thank you.
Then.
Is cached regions determined by address bit 31 set like the below in spec when dmmu is disable.?.

Spec says uncached regions define by address bit 31 when dmmu is off.
and When dmmu is on, it is possible for any address to be cached or not.

The following is context in spec.
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3.3.12. Data Cache inhibit with address bit 31 set
If DMMU is disabled, by default all addresses with bit 31 of the address asserted high will cause the data cache to be inhibited, meaning no reads or writes are cached.

If the DMMU is enabled, it is possible for any address to be inhibited or not, and in these modes the cache behaves accordingly.
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Is correct this spec'contect ?
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