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OpenRISC Multi-core?
by mvanga on Oct 1, 2012 		mvanga
Posts: 1
Joined: Nov 9, 2011
Last seen: Oct 1, 2012
Hi all,

I was wondering if anyone has worked on a multi-core version of OpenRISC (using cache coherent shared memory). Is there any work on this? I found one thread about a researcher at EPFL but he doesn't seem to be active there any more.

Also, as a separate question, how many OpenRISC cores could one theoretically run on a latest-and-greatest FPGA platform available on the market today (assuming very few peripherals of course)?

Thanks and best regards!
/mvanga
RE: OpenRISC Multi-core?
by jeremybennett on Oct 1, 2012 		jeremybennett
Posts: 815
Joined: May 29, 2008
Last seen: Jun 13, 2019

Hi mvanga

Stefan Wallentowitz at the Technical University of Munich (TUM) has worked on this.

HTH

Jeremy

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RE: OpenRISC Multi-core?
by wachag on Oct 3, 2012 		wachag
Posts: 6
Joined: Feb 3, 2010
Last seen: Oct 12, 2013
On a Digilent Atlys (Spartan 6, xc6slx45), 4-6 OpenRISC core seems reasonable.
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