hi everyone,
I am using DC(Design Compiler) tool for ASIC synthesis of OR1200. While doing this i am getting these warnings :
1. 'Case' statement is full and has only one nontrivial branch; it will be inlined.

2. or1200_wb_biu.v:193: 'wb_fsm_idle' is being read, but does not appear in the sensitivity list of the block.

3. ram_wb_b3.v:249: Value of function 'set_mem32' is used before being assigned; the synthesized result may not match simulations. (ELAB-393)

4. or1200_sb_fifo.v:108: signed to unsigned conversion occurs.

Also i am seeing some non-synthesisable code in the RTL. How can RTL have non-synthesisable code?

Please suggest the way do avoid these warnings?

--Sudhanshu Billore

regarding Question:2
you have to put 'wb_fsm_idle' in the sensitivity list of always block(if its a combo logic)

q3) ELAB-393

"A Verilog function definition implicitly declares a variable, internal to the function, with the same name as the function. You receive this warning message when the function returns without the variable having been assigned or when the variable is read by the function body before the variable is assigned"

Q4)signed to unsigned conversion: you have to check corresponding code..

Q5) RTL code may contain some non-synthesize code like display statements/ initial statements for debug purpose only. Any how they will be ignored during synthesis.

You do not want to synthesize block srams in an asic. Your asic vendor will provide you with hard macros that you must instantiate to replace the generic sram model. This will involve changing some `define values to point toward your asic process.

John Eaton