Hii,

We as a group are working on SOC with openrisc 1200 as a central processor. I know it has Wishbone interface but I want to implement it using AMBA bus. So can i do it and what modification I have to make in this regard?

Thanks

Hi there, I actually had a similar problem a few years ago: I had an AMBA bus connected processor (Toshiba MeP) but I wanted to use the I2C core from OpenCores with the wishbone interface. I ended up implementing a simple bridge in Verilog to adapt the I2C wishbone interface. My version was a very quick and dirty implementation done in a day for a university research project.

Your best bet it to start with the Wishbone interface specification and the AMBA specification then try implementing slave and master shell cores with each. Once you have a feel for how the master and slave interfaces work, you can implement a Wishbone-to-AMBA or AMBA-to-wishbone bridge in verilog. Proper targeting of the OpenRISC to AMBA is a rather big undertaking however because you have to understand the processor implementation first to change it. If you are using the OpenRISC as a means to an end and a <10 MHz difference in speed is not a problem, the bridge should work well enough.

James
https://www.jamestandon.com

Hii ,

If I use a bridge then , will it effect the throughput of the processor ?