I have proceeded as mentioned in http://minsoc.com/1_0:synthesis

But the "make all" step fails with the following error message :

Compiling verilog file "/home/aurabindo/minsoc/prj/../prj/xilinx/or1200_top.prj" in library work
ERROR:HDLParsers:3464 - Library work mapped to physical location xst/work does not exist.
ERROR:HDLCompilers:219 - Open of logical library 'work' failed
Analysis of file failed.

The full log is here : http://pastebin.com/eNu7KMqW

Have anyone came across this error ?

Thanks in advance,
Aurabindo

Can you pastebin the results of doing a "make distclean" followed by a "make or1200"?

I`m getting the same error. http://pastebin.com/6UNr4RfL

Hello Aurabindo,

did you download minsoc using Subversion following the wiki guide?

Even if you did, maybe or1200 is missing. Try to list the files from the directory:
ls minsoc/rtl/verilog/or1200/rtl/verilog/

Regards,
Raul

Thank you Raul for the reply, but the or1200 source files are all there i guess.

http://pastebin.com/SYK0Ur2Z



Should I use another version of ISE? I`m using 13.2 ?

Or maybe another revision from CVS ?


Best Regards,
Aurabindo

Hello again Aurabindo,

I hope you are still interested, I didn't find the time to log in.

Could it be that you don't have permission to write to the minsoc/syn/xst directory? That could happen if you run make as root and then as user or if you installed minsoc as root.

This is the first time I see this problem.

Regards,
Raul

Hi Raul, I`m still working on it. First problem is now solved. OR1200 source files were there, but it got corrupted somehow. I downloaded it again and now synthesis is working :)

But still, there is a make error "30". I did "make all" in minsoc/syn/. It says there is one unrouted signal. Terminal output is here : http://pastebin.com/r99WuPVP

I tried to launch the xilinx router tool manually ( _fpga_editor ). But it says "error while loading shared libraries: libFed_Engine.so: cannot open shared object file: No such file or directory". But I did run settings32.sh for ISE. However, xst was working fine.

Here is the contents of minsoc_par.unroutes http://pastebin.com/KkyNJXYw

Did I miss some configuraions ? How am I supposed to manually route them ?

Hello again,

did you replace or1200 with a newer version? Minsoc 1.0 works with or1200 rel1 and patches it.

I'd checkout minsoc 1.0 again and run the setup:
http://www.minsoc.com/1_0:configuration

I gave it a break for some time, and tried it today. Completely fresh install of minsoc. Toolchain was also built automatically by minsoc script on a fresh fedora18. Still the same error of one signal not routed. It is this one :

or1200_top/or1200_du/Mcompar_match0_cmp_eq0003_cy/ProtoComp37.GNDF.0


If I run the make again, it would create bit file. I dont know if it would work. What do you think ? [need to go to my college to test it on hardware, but we`re on vacation].

Few more questions: I`m using ISE 13.2. How am i supposed to use the included .prj and .xst files to use it with ISE`s GUI ? Because in the terminal it asks me to try opening it in FPGA editor and manually route it.

Regards,
Aurabindo

Hello again, I tried it with Spartan 3a dsp kit and worked. But not for Spartan 3e starter. Guess default Minsoc setup is too much for spartan3e.