Hello all, When i try to integrate OR1200 Processor with Peripherals and Bus Modules in Xilinx ISE there are lot of warnings about 3000 and later i see a lot of modules getting trimmed off and improper device utilization summary.Also synthesis of standalone processor is giving expected results. Few Warnings are pasted below Register in unit has a constant value of 00000000000000000000000000000000 during circuit operation. The register is replaced by logic. WARNING:Xst:1780 - Signal is never used or assigned. Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . I cross checked the ifdef to confirm that MACROs are properly defined and included in include path of Project and defined properly in or1200_defines.v file. I guess synthesis tool is unable to get the file properly... any suggestions to get the processor synthesized correctly without warnings..? Ganesh