Hi community,

first some details about my setup:
- FPGA: Spartan-6 (XC6SLX150), on Board Opal-Kelly XEM6010
- Cable: Xilinx DLC9G (working, but slow, sometimes problems with initialization)
- Cable: Olimex ARM-USB-OCD-H (FT2232H based, NOT working, yet)
- Windows XP, Cygwin, MinSoC release 1.0
- adv_jtag_bridge (the version installed by MinSoC)

Now I'm trying to get the Olimex-Cable to work.
- the cable has the 20-pin ARM pinout
- I connected only VREF, GND, TDI, TMS, TCK, TDO to my board
- other pins of the cable are floating (NTRST, RTCK, RST, DBGRQ, DBGACK), they should be unused by adv_jtag_bridge (hopefully).

Now, if I run adv_jtag_bridge ft2232 -v 15ba -p 2b, I get
Devices on JTAG chain:
Index Name ID Code IR Length
----------------------------------------------------------------
0: (unknown) 0x7403D093 -1
1: (unknown) 0x4002007F -1
2: (unknown) 0xFFFFFFFF -1
3: (unknown) 0xFFFFFFFF -1
[continues until 1023�]

The strange thing is, that the first device ID is nearly correct. The expected ID is 0x3401D093. There is NO second device on the chain.

My first idea was that the JTAG clock rate is too fast (as my cable uses FT2232H, which is a faster version).
So I played around with cable_ft2232.c, line 447 and lines 829+830.
But no success� Above results are always reproducible. Even the same IDs all the time. Even for another board (same model, I have several of them).

As a side-note: I have another FPGA (Spartan-3) with expected ID 0x41434093, which is found as 0x01434093 by adv_jtag_bridge. However, this board sometimes results in other IDs.

Do you have any idea where to start finding the problem?

Thanks a lot!
Hagen

Hm, I really don't know what is going wrong here, but I found a solution:

The following patch is needed in chain_commands.c:



It seems that the left bits of temp_manuf_code are not zero as they should be.
As a consequence, the device ID of my chip is read incorrectly, and the end of the chain cannot be detected. This single line fixes the problem and should not do any harm in other cases...

Regards
Hagen

Hello Hagen,

the problems with the Xilinx USB cable are known and have been solved on Advanced Debug System release 3. It did not make it to minsoc 1.0, but you only have to update the adv_jtag_bridge:

cd minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge
svn switch http://opencores.org/ocsvn/adv_debug_sys/adv_debug_sys/tags/ADS_RELEASE_3_0_0/Software/adv_jtag_bridge
make
make install

That is probably a more comfortable solution to you. I updated the FAQ accordingly:
http://www.minsoc.com/advanced_jtag_bridge_faq?&#adv_jtag_bridge_does_not_connect_to_xpc_usb_why

I hope that helps,
Raul

Hi Raul,

thank you for your information.
The new version of the Advanced Debug System actually solves the initialization as well as the speed issue for the DLC9-Cable.

But my original question with the FT2232-based cable is not solved.
My patch is still applicable, and fixes the enumeration-issue which I described in the first post.

Keep up the great work!

Hagen

Hagen -

Agreed, your patch is correct and will be included in the next release of adv_jtag_bridge.

Nathan