Hello!

My name is Sergey Marfin and currently I am trying to port orpsoc to VC707 Virtex-7 Xilinx board.

I have already tried and have successfully built minsoc for it, had some UART issues, but AdvDebug worked fine through a Platform Cable USB.

I am having some question regarding porting. As it seems, the Atlys Diligent board has the most common peripherals with my board.

I would like to start with just a uart, a debug interface and GPIO.

So, questions:

1) Considering modyfing atlys sources, what files and defines should I modify. In minsoc it was the memory defines (BRAM), the BSCAN JTAG defines (which I cannot find in orpsoc), the board.h file, the ucf constraints file, and defines of target FPGA (which I cannot find as well, those are critical for compilation).
2) How should I generate clocks? Is it a good idea to use Xilinx Clock Wizard in CoreGen?
3) Could you please outline how should I modify the DDR2 wrapper to use DDR3 MIG core interface?
4) If it is not that difficult, could someone explain to me the general process of porting orpsoc to other boards? I have multiple, but no support for them whatsoever.

Thanks in advance, I have a lot more questions though.

Happy synthesizing!

System specs : Ubuntu 12.10 Linux x32, ISE+Vivado 14.3, vc707 development board