Dear all,

I managed to build a minsoc with all the source code provided on my de2(ep2c35), and I established the adv_jtag_bridge successfully HWP server port 9928 and JSP server port 9944, for obtain JSP server I change JSP_MULTI_DEVICE_CHAIN=true in /minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/Makefile, then I use a telnet terminal for do the connection # telnet localhost 9944

After that, I use or32-elf-gdb to download the minsoc/sw/uart/uart.or32 program into the minsoc, it displayed some information about the sections and the address. (image attached)
When I continue the process like below:
(gdb)target remote :9999
0x00000010 in ?? () (Is it a wrong direction? what I have to do?)
(gdb)load
(gdb)set $pc=0x100
(gdb)c
Then does nothing in the telnet terminal. With no more information displayed.

I wonder why this happen and what can I do.

Most thanks.

Hello Fernandw,

the JSP is not in the same address space of UART. In order to support both, I included a JSP firmware under minsoc development.

Furthermore, the JSP hardware has to be correctly included in the system. That was also done for the development version but not for 1.0.

Regards,
Raul

Thanks Raul for your quick response.

I am replying to this day because some days ago I had internet problems.

I downloaded the Development version with the JSP and configured to my DE2-70 board, then: Installation OK, Simulation OK, Synthesize OK, but Software Upload and Debugging FAIL (NO HWP server on host) (attache image)

I searched hpw_server.c (line 150) but not even understand what's going on.

Could you advise me, please.

The HWP server didn't start because there's no watchpoint hardware in your CPU. This is not a problem, because all of the regular debugging via GDB will still work fine. The RSP server that GDB attaches to is running, as is the JSP (JTAG serial port) server. Try to connect GDB as the instructions say, I suspect it will work fine.

Hi nyawn! Thanks for the explanation, I read the "adv_jtag_bridge Doc" too.

My summary is the next:

-MinSoC Development version
-Installation OK
-Confure my Altera DE2-70 (with JSP) OK
-Synthesize OK
-Software Upload and Debugging
(I tried with)
#adv_jtag_bridge usbblaster ( in /home/fernandw/ the place with the .bsd File for my board)
#adv_jtag_bridge ft245
#adv_jtag_bridge -b /home/fernandw/ usbblaster

#telnet localhost 9944 OK

GDB (I always receive)
(gdb) target remote :9999
Remote debugging using :9999
or32_exit (i=10) at support.c:35
35 while (1);
or
(gdb) target remote :9999
0x0000001c in ?? ()
Then nothing happen after load, set pc, c appears Continuing and the telnet doesn't show nothing.

I tried a test "# adv_jtag_bridge -t usbblaster" SRAM test passed, Starting CPU0! result = deaddeb5 (different than deaddae1 in the or32_selftest.c) so Self-test FAILED. I tried to understand the code in or32_selftest.c but is difficult is a lot. I can't advance.
With your experience, could you advise me? please.

If the self-test fails at the final check, then I would guess that you are using the OR1200 version 3. There is a known bug using that version of the CPU with adv_jtag_bridge. The OR1200v1 does not have the bug, you might try that version.

Beyond that, it's very difficult to debug the problem without input. Have you tried a simple assembly program to blink an LED on the development board? Try the simplest thing possible to get any kind of output from the program running on the OR1200. Once you know the software is running, you can add complexity a bit at a time until you find the part that doesn't work.