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no use no use 1/1 no use no use
change the simulator to NC-Verilog simulation problem
by versatileman on Dec 7, 2012 		versatileman
Posts: 1
Joined: Oct 15, 2012
Last seen: Nov 15, 2014
hi,all
i modify the orpsocv2/sim/bin/Makefile, and change the default simulator Icarus Verilog to the Candence's NC-Verilog. When i run in the orpsocv2/sim/run:
make rtl-test or1200-simple, the or1200-simple.vmem can be produced, but the ncverilog Compiling will has error :

make: *** [vlogsim.elf] Error 1
I cannot figure it out.

thanks to anyone who can give me any information
no use no use 1/1 no use no use
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