Hello all,

I am working on porting the OR1200 to a ML605 board. Unfortunately, I don't have modelsim and cannot run in the linux environment so I imported the rtl into Xilinx ISE and have started to work on this. After looking into a DDR3 controller and finding relatively little, I decided to just use internal RAM for now because I'm looking to really just use the processor as a sequencer for other logic.

I used the ML501 build tree as a starting point. I then commented out most peripherals using the orpsoc-defines.v file and remapped all of the CLOCK, GPIO, UART, etc. pins in the UCF. I also had to instantiate a new clock controller (MMCM) because DCMs are not on the Virtex 6. I was getting timing errors when running up at 66.666MHz so I just decided to drop the clock speed to see if I could get something working. I found that I was able to run at 22.222MHz.

Right now there is no bootloader. I just use the ORSoC debugger to stop the processor and load code into RAM using GDB and or_debug_proxy in linux. The problem is that sometimes after making small changes to the build the whole thing stops working. I've added a heartbeat (which is just a counter connected to a LED) to show me whether the clocks are working when the processor isn't. Also, when it breaks GDB thinks that it has successfully loaded the code but it won't run. When I probe the memory manually to see if the RAM has been written sometimes the data looks valid and other times its

either zero or gobbledygook. This says to me that either the RAM has timing errors or the dbg_if/jtap_tap has timing errors. Also, if I synthesize the RAM by itself xst seems to think it can run somewhere in the 250MHz range which seems logical since it is just instantiating block RAM with some control logic.

So I decided to check the timing reports and found that the dbg_if is completely unconstrained. dbg_if0 and jtap_tap0 both have two unrelated time domain clocks, the jtag_tck jtag clock and the wisbone clock, wb_clk. Most of the unconstrained paths that I see are between these two time domains. I understand that many times leaving paths unconstrained in a correctly designed system won't matter, but has anyone seen a necessity for it? In general, it's good practice to constrain all nets even if just telling the compiler to ignore the timing. I'm not sure this is the issue, but I feel it is noneless an issue that should be addressed.

If I can get this working I will make every effort to add my work to the tree, but right now I seem to be having implementation problems. Any help on this matter would be most apprecited.

- Bryce B.

P.S. For the life of me I can't seem to find a way to search for posts in the forums. Are we just supposed to search with google?