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VHDL testbench Help
by saraershadi on Jan 26, 2013
saraershadi
Posts: 1
Joined: Sep 10, 2009
Last seen: Jul 31, 2016
Hi all,

I want to test a module in VHDL text bench . I want to reda from file and write the result to a text file.

How can I do it with text file in VHDL test bench .
Thanks alot
no use no use 1/1 no use no use
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