Hi, I am trying to use the openrisc processor on an ACTEL FPGA.

As you know, there is no native support for Actel as of yet, so I am having some trouble getting the CPU to work and I desperately need some help.

First I will briefly say what I have tried thus far and the results I have gotten.
Since Actel isn't supported by the tools provided yet, I am attempting to synthesize the design using Libero and Synplify Pro.


When trying to synthesize the normal ORPSoC project (without changing any defines etc.) then Synplify can't synthesize it. This is because it runs out of memory while trying to synthesize it, which indicates that the design would be much too large to fit onto any FPGA in any case. This is probably because ORPSoC tries to implement the RAM by using flip flops instead of using the on-board RAM provided (which would need a technology specific design in order to be used I am assuming).


When commenting out //`define RAM_WB, ORPSoC synthesizes with the following amounts:
Core Cells: 8027
IO Cells: 8
Block RAMs: 4

This seems much too small and I really don't trust that it would work at all. I am not really sure how not defining RAM can make the design so small? Surely the CPU etc. should still be synthesized, or am I missing something?

This made me try minSoC, which also runs out of memory with the standard design. When commenting out //`define OR1200_QMEM_IMPLEMENTED, it does synthesize but also much too large with:
Core Cells: 609836
IO Cells: 10
Block RAMSs: 0

Finally I turned to the plain OR1200 implementation.
This I got to synthesize with acceptable values, which gave me hope that it is possible to get OR1200 to work on Actel without rewriting all the code. It synthesizes with the following values:
Core Cells: 13823
IO Cells: 381
Block RAMs: 48

As you can see, these values are much more acceptable and fits onto the device. This brings me to the next problem: the documentation about the OR1200 doesn't give me enough information to know how to program the OR1200 with other software, or how to test that it works as expected.

I have been going through the code for days now trying to figure out where the memory is defined in which the program is stored and loaded from, but haven't been able to pin point it yet. I would also like to write a testbench to see if the CPU is working as it should, but I am not sure which signals to apply to the pins or what reaction to expect.

So to sum up my questions:
Firstly, is there some way that I have missed that anyone can think of to make ORPSoC work on an Actel device(preferably by using Actel tools like libero and synplify etc.)

Secondly, can someone please let me know how the program memory of the OR1200 works, and also which verilog file it is defined in?

And thirdly, what signals can I send the CPU in a testbench to test if it is working as it should?

If there is documentation out there that provides the information I am looking for then a link would also be much appreciated. I find the website a bit confusing at the moment haha.

Thanks in advance for any help provided!


(P.S. I have also tried and succeeded in synthesizing mor1kx, and I find the code there easier to understand, but the documentation is once again not good enough for me to know what to do next, so I thought the plain OR1200 might have a better chance of support)

OpenRisc is all handcrafted verilog code so anything like that is going to be a labor of love. Your best bet is to see what other fpgas had to do and use that as your starting point. Anything other than changing `define values will require some work.

I have had some success with loading program code into QMem and running it from there but it took quite an effort and would be hard to merge back into the trunk.


All code is loaded through a readmemh statement so search for that to see where you have to place your binary file for simulation and synthesys.

The best way to test it is write a simple program that receives a uart character, increments it and then echoes it back. If you can do that then you can do anything.


John Eaton

Thanks for the reply John.

I used grep to search through all the verilog source files looking for readmemh, and couldn't find one instance of the function. MinSoC did have it, but not OR1200.


Does the verilog code include the program memory for OR1200? Or does it assume that the memory is stored externally and fetches it from there? Also could you please tell me the verilog file name where this is handled?

Thanks in advance for your help.
Kind Regards
Francois

Hi,

We actually have a port of ORPSoC for a board with an Actel ProASIC FPGA. It used to be sold at the webshop, but it's out of stock now http://opencores.org/shop,item,4

Take a look in the boards/actel directory of orpsoc and see if you can find anything useful in there. The build scripts uses synplify and libero, which seems to be what you are interested in. The ordb1a board uses an external SDRAM for memory, so you would need to find a controller that works for your board.

I could try to dig up some old numbers and see roughly what the resource usage would be for that board, but I don't have the toolchain installed, so I can't do a test build at the moment.

Regarding the actual program loading, we are aware that the documentation is a bit scattered, and a good step-by-step tutorial is high of our list of priorities.

What basically happens at startup is that after reset is released, or1200 tries to read an instruction from the address defined by the boot_adr parameter (this is normally address 0x100 if nothing else has been supplied)

So your first priority should be to see that the clock is running, reset is released and that or1200 fetches an instruction on the instruction bus from address 0x100.

orpsoc also provide a test bench that can compile and load assembler and C programs, or run compiled elf files directly. There are some test cases in the orpsoc sw/tests directory that can be run in a simulator. (Modelsim, Icarus Verilog and Verilator are supported simulators)

You can run a test case by entering sim/run in orpsoc and type make rtl-test TEST=or1200-basic (to run the or1200-basic test case) or make rtl-tests to run them all.
This is better explained in the orpsoc documentation pdf in the doc directory.

I realize that this answer is becoming a bit longer than I expected, but don't hesitate to ask for more information or clarifications if you need

Good luck!

--
Olof Kindgren
______________________________________________
ORSoC
Website: www.orsoc.se
Email: olof.kindgren@orsoc.se
______________________________________________
FPGA, ASIC, DSP - embedded SoC design

Hi, thanks very much for the information. I don't mind long replies at all, the more information the better!

I took a look at the board you suggested and it helped a lot, but I am still struggeling with a few things. I prefer to work in windows because I can't seem to get Libero to work at all in Ubuntu. I think the floating license that you are forced to use with linux is most probably part of the problem, but that aside at least modelsim seems to work more or less correctly (with the license) so maybe its something else.

Anyway, I tried to run the scripts with cygwin at first, but to no avail as the scripts seems to be specifically aimed at linux. I then tried on ubuntu and got quite a lot further, but in the end I got the following errors:


### Launching simulation ###

Reading /usr/local/actel/Libero_v9.1/Model/modeltech/tcl/vsim/pref.tcl

# 6.6d

# vsim -do {set StdArithNoWarnings 1; run -all; exit} -c -quiet -suppress 8598 orpsoc_testbench
# // ModelSim ACTEL 6.6d Nov 2 2010 Linux 3.2.0-38-generic-pae
# //
# // Copyright 1991-2010 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND
# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# // AND IS SUBJECT TO LICENSE TERMS.
# //
# ** Error: (vsim-3033) /home/francois/ORPSoC1/ORPSoC/boards/actel/ordb1a3pe1500/sim/run/../../../../../rtl/verilog/smii/smii_if.v(264): Instantiation of 'GND' failed. The design unit was not found.
# Region: /orpsoc_testbench/dut/smii0/smii_if0
# Searched libraries:
# /home/francois/ORPSoC1/ORPSoC/boards/actel/ordb1a3pe1500/sim/run/work
# ** Error: (vsim-3033) /home/francois/ORPSoC1/ORPSoC/boards/actel/ordb1a3pe1500/sim/run/../../../../../rtl/verilog/smii/smii_if.v(266): Instantiation of 'CLKDLY' failed. The design unit was not found.
# Region: /orpsoc_testbench/dut/smii0/smii_if0
# Searched libraries:
# /home/francois/ORPSoC1/ORPSoC/boards/actel/ordb1a3pe1500/sim/run/work
# ** Error: (vsim-3033) /home/francois/ORPSoC1/ORPSoC/boards/actel/ordb1a3pe1500/sim/run/../../../../../rtl/verilog/smii/smii_if.v(443): Instantiation of 'CLKDLY' failed. The design unit was not found.
# Region: /orpsoc_testbench/dut/smii0/smii_if0
# Searched libraries:
# /home/francois/ORPSoC1/ORPSoC/boards/actel/ordb1a3pe1500/sim/run/work
# ** Error: (vsim-3033) /home/francois/ORPSoC1/ORPSoC/boards/actel/ordb1a3pe1500/sim/run/../../rtl/verilog/sdc_controller/sd_clock_divider.v(16): Instantiation of 'CLKINT' failed. The design unit was not found.
# Region: /orpsoc_testbench/dut/sdc_controller_0/clock_divider_1
# Searched libraries:
# /home/francois/ORPSoC1/ORPSoC/boards/actel/ordb1a3pe1500/sim/run/work
# Error loading design
Error loading design


As far as I can tell this error means that it can't find the design units for the actel specific blocks. I actually found these blocks in precompiled format, and tried a few methods of including them, but without knowing how the scripts work I couldn't figure out what to change in the scripts for them to be included. Is there a document somewhere that explains how the scripts work?

I then went back to windows to try another method. I thought if I could just manually do what the scripts do then it should work. The problem is that I don't really know what the scripts do, but in any event I just imported all the files from the project into libero, replacing all generic files with their board specific counterpart if there was one.

This seems to be working to a certain extent. The design synthesizes correctly and with reasonable size. The only problem now is that I am not sure how to go further in simulating what the scripts do. I am still not sure how to write a program that can be loaded into the cpu, or how to test if this design is working as it should.

I see there is an orpsoc_flashROM.v file with the following contents:

module orpsoc_flashROM(CLK,ADDR,DOUT);
input CLK;
input [6:0] ADDR;
output [7:0] DOUT;

wire U_7_PIN2;

GND GND_1_net(.Y(U_7_PIN2));
UFROMH #( .MEMORYFILE("devboard_flashROM.mem"), .ACT_PROGFILE("devboard_flashROM.ufc")
) UFROM0(.CLK(CLK), .DO0(DOUT[0]), .DO1(DOUT[1]), .DO2(
DOUT[2]), .DO3(DOUT[3]), .DO4(DOUT[4]), .DO5(DOUT[5]),
.DO6(DOUT[6]), .DO7(DOUT[7]), .ADDR0(ADDR[0]), .ADDR1(
ADDR[1]), .ADDR2(ADDR[2]), .ADDR3(ADDR[3]), .ADDR4(
ADDR[4]), .ADDR5(ADDR[5]), .ADDR6(ADDR[6]));

endmodule


I am assuming (and of course I might be wrong) that this is probably where the programming file is loaded? Could someone please shed some light on what is happening in this file?

Sorry about the long post. I just want to provide as much information as possible to help anyone help me. So to sum up what I currently need to know:

What exactly does the scripts do? (If there is already documentation then just a link would suffice, but I couldn't find any).
Is it possible to manually do the steps done by the scripts by using libero, synplify and the other actel tools?
Is it possible to make the design work by just using the hdl files and relying on the actel tools to do the rest?
And lastly, where in this design is the program file stored? (I know you said above that it is stored on external memory, but surely there must first be some bootloader program to tell the CPU where it is?)

Thanks again for any help!
Kind Regards
-Francois

I have another shorter but also memory related question:

In the top verilog file of ORPSoC for ordb1a3pe1500 board they instantiate the following memories (that I can tell).

Versatile SDRAM

ROM

FLASH ROM

RAM_WB

Could someone give a bit more information as to what each of these memories are used for? As far as I can see only the ROM and FLASH ROM seems to be absolutely neccesary, but still not sure which one is used for what purpose. And not sure at all what versatile SDRAM is needed for or RAM_WB.

Help!, I am trying to use the openrisc processor on an ACTEL FPGA.

Please tell me if I understand a solution among FNolte, everybodies.
Use environment: Open RISC Actel ORDB1A3PE1500
�path : /ORPSoC/boards/actel/ordb1a3pe1500/sim/run
command: > make rtl-tests MGC_NO_VOPT=1

It becomes a result same as the contents which FNolte describes, and ModelSim "Error loading design "message appears,
and the compilation result is finished before ModelSim start. (the following message)
It wants to be settled somehow.
�What kind of procedure did you solve this Error in; thanking you in advance?
(if this works well, I think that Actel development environment construction is the end)

------------Error Message contents - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
### Launching simulation ###

Reading /usr/local/actel/Libero_v9.1/Model/modeltech/tcl/vsim/pref.tcl

# 6.6d

# vsim -do {set StdArithNoWarnings 1; run -all; exit} -c -quiet -suppress 8598 orpsoc_testbench
# // ModelSim ACTEL 6.6d Nov 2 2010 Linux 3.2.0-38-generic-pae
# //
# // Copyright 1991-2010 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND
# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# // AND IS SUBJECT TO LICENSE TERMS.
# //
# ** Error: (vsim-3033) /home/francois/ORPSoC1/ORPSoC/boards/actel/ordb1a3pe1500/sim/run/../../../../../rtl/verilog/smii/smii_if.v(264): Instantiation of 'GND' failed. The design unit was not found.
# Region: /orpsoc_testbench/dut/smii0/smii_if0
# Searched libraries:
# /home/francois/ORPSoC1/ORPSoC/boards/actel/ordb1a3pe1500/sim/run/work
# ** Error: (vsim-3033) /home/francois/ORPSoC1/ORPSoC/boards/actel/ordb1a3pe1500/sim/run/../../../../../rtl/verilog/smii/smii_if.v(266): Instantiation of 'CLKDLY' failed. The design unit was not found.
# Region: /orpsoc_testbench/dut/smii0/smii_if0
# Searched libraries:
# /home/francois/ORPSoC1/ORPSoC/boards/actel/ordb1a3pe1500/sim/run/work
# ** Error: (vsim-3033) /home/francois/ORPSoC1/ORPSoC/boards/actel/ordb1a3pe1500/sim/run/../../../../../rtl/verilog/smii/smii_if.v(443): Instantiation of 'CLKDLY' failed. The design unit was not found.
# Region: /orpsoc_testbench/dut/smii0/smii_if0
# Searched libraries:
# /home/francois/ORPSoC1/ORPSoC/boards/actel/ordb1a3pe1500/sim/run/work
# ** Error: (vsim-3033) /home/francois/ORPSoC1/ORPSoC/boards/actel/ordb1a3pe1500/sim/run/../../rtl/verilog/sdc_controller/sd_clock_divider.v(16): Instantiation of 'CLKINT' failed. The design unit was not found.
# Region: /orpsoc_testbench/dut/sdc_controller_0/clock_divider_1
# Searched libraries:
# /home/francois/ORPSoC1/ORPSoC/boards/actel/ordb1a3pe1500/sim/run/work
# Error loading design
Error loading design