I'm working with OpenRISC for a project at University Of Bologna.
I noticed that there are some margins of micro-architectural
improvements in the current version of the OR1200 processor. For example:

- Load/store operations are blocking. The cost of a memory access is always at least 2 clock cycles, even if the data to access is in the qmem and there are no data dependencies between the load and the following operations.
- The multiplication is also blocking, and every time a multiplication is called the processor always stalls for 4 cycles.
- another improvement that came in my mind and is implemented in many embedded microprocessors is the hardware loop.

Does anybody know if there has been some kind of developement in this direction?

Hi,

We are collecting ideas for an improved OpenRISC architecture (currently called or2k). Some of these ideas were discussed at the last OpenRISC project meeting, last october.
You can find some more information here http://opencores.org/or2k/OR2K:Community_portal

Unfortunately, there hasn't been much progress on this side, as we have been busy with GCC, binutils, LLVM, improved debugging support, OS ports, new build systems and god knows what more :)

But more ideas are welcome, so feel free to post ideas on the discussion page or join us at #openrisc on irc.freenode.net and discuss some ideas

--
Olof Kindgren
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ORSoC
Website: www.orsoc.se
Email: olof.kindgren@orsoc.se
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FPGA, ASIC, DSP - embedded SoC design

The first two of the optimizations aren't really openrisc architecture specific, but only limitations in the or1200 implementation.
The third one is more of architectural nature.