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OpenRISC on XuLA2
by mbenson on Mar 18, 2013 |
mbenson
Posts: 1 Joined: Mar 15, 2013 Last seen: Apr 10, 2013 |
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I would like to put an OpenRISC SoC on a XuLA2 board (http://www.xess.com/prods/prod055.php), with a Spartan 6 LX25. I'm very new to FPGA's. Could somebody let me know if my strategy is sound or already doomed to failure?
I'm starting with the orpsoc2, Xilinx Atlys board. I copied the atlys directory to "xula2" and created a xula2 build. The XuLA2 has SDRAM, not DDR SDRAM, and the Xilinx Core Generator apparently does not support SDRAM. So I disabled the Xilinx MIG controller, and ran ISE to verify at least that fits. Implement completed with 1 timing error. I'm rerunning it with a slower clock speed. Once this works, I'm going to replace the MIG controller with the "8/16/32 bit SDRAM Controller" core. Does this sound correct? |
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RE: OpenRISC on XuLA2
by lollisoft on Apr 6, 2014 |
lollisoft
Posts: 3 Joined: Jan 15, 2009 Last seen: Apr 8, 2015 |
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I would like to put an OpenRISC SoC on a XuLA2 board (http://www.xess.com/prods/prod055.php), with a Spartan 6 LX25. I'm very new to FPGA's. Could somebody let me know if my strategy is sound or already doomed to failure?
I'm starting with the orpsoc2, Xilinx Atlys board. I copied the atlys directory to "xula2" and created a xula2 build. The XuLA2 has SDRAM, not DDR SDRAM, and the Xilinx Core Generator apparently does not support SDRAM. So I disabled the Xilinx MIG controller, and ran ISE to verify at least that fits. Implement completed with 1 timing error. I'm rerunning it with a slower clock speed. Once this works, I'm going to replace the MIG controller with the "8/16/32 bit SDRAM Controller" core. Does this sound correct? Hi, I am also interested in OpenRISC SoC and XuLA2. Do you got any success and project file up and may share? Thanks, Lothar |
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