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or1200 test case
by sudhanshubillore on Mar 18, 2013
sudhanshubillore
Posts: 16
Joined: Aug 10, 2012
Last seen: Jun 2, 2015
Hi all,
I am working on OR1200 processor. I modified current cache architecture of or1200 to 4-way set associative cache architecture.
I modified both IC & DC cache. Now I am trying to run all existing test cases by disabling IC & DC just to ensure while modifying IC & DC I didn't disturb other modules.
I found "or1200-dsxinsn" test case is not getting over, when I am terminating it through ctrl+c then message like "unspecified location accessed" is coming.
Please suggest how to debug it?
How to debug such an exception related problems?
Thank You.

regards,
Sudhanshu Billore
RE: or1200 test case
by stekern on Mar 19, 2013
stekern
Posts: 84
Joined: Apr 28, 2009
Last seen: Nov 10, 2016
You can generate a VCD by running the test with:
make rtl-test TEST=or1200-dsxinsn VCD=1
RE: or1200 test case
by sudhanshubillore on Mar 20, 2013
sudhanshubillore
Posts: 16
Joined: Aug 10, 2012
Last seen: Jun 2, 2015
I generated VCD file and I am able to see waveforms too. There I found "if_pc" signal is suddenly changed from 0x130 to 0x1000. I am not sure is this the correct signal I am looking at. It seems it is an exception, even if I know it is an exception then how to resolve it? How to go to exact root of the problem?
RE: or1200 test case
by stekern on Mar 20, 2013
stekern
Posts: 84
Joined: Apr 28, 2009
Last seen: Nov 10, 2016
Your problem has nothing to do with that, it's simply an oversight in the
or1200-dsxinsn test when caches are disabled, this http://pastie.org/6638818 patch fixes it.
RE: or1200 test case
by sudhanshubillore on Mar 28, 2013
sudhanshubillore
Posts: 16
Joined: Aug 10, 2012
Last seen: Jun 2, 2015
Hi,

Here is the combination which I use & corresponding results.
I hope with table problem is very much clear.
First of all I am not able to understand whats the need of that patch? What its purpose?
Please help me out..
Thank you.
---------------------------------------------------------------------------------------
combination dsxinsn testcase ticksyscall testcase
---------------------------------------------------------------------------------------
1.DC & IC(disable) test is ok infinite loop
(with patch)

2.DC & IC(disable) infinite loop infinite loop
(without patch)

3.DC & IC(enable) ERROR 1 test is ok
(with patch) (checking simulation results....)

4.DC & IC(enable) ERROR 1 test is ok
(without patch) (checking simulation results....)
RE: or1200 test case
by stekern on Mar 30, 2013
stekern
Posts: 84
Joined: Apr 28, 2009
Last seen: Nov 10, 2016
The purpose of the patch is to fix the test, which was broken.
The patch have now been committed to SVN too.

I'm not sure I understand what you mean with ERROR and 1 test is ok in:
---
3.DC & IC(enable) ERROR 1 test is ok
(with patch) (checking simulation results....)

4.DC & IC(enable) ERROR 1 test is ok
(without patch) (checking simulation results....)
---

is that with your cache changes applied or without?
if so, they're obviously not working correctly (yet) ;)
If not, I don't know, the test passes here with caches enabled
before and after that patch.
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