Hello,

I want to run simulation of openrisc rtl using Xilinx isim.
To do so, i used the great tutorial from Sven-Ake Andersson (thanks again) ; tutorial i found at this adress :
http://www.rte.se/blog/blogg-modesty-corex/simulating-orpsoc-using-isim/2.4

i downloaded and used "as is" the file "orpsoc_sim.prj" wich contains path to verilog files used for simulation.

i followed the tutorial and then i used the command to run simulation using xilinx executable named "fuse" :
fuse work.orpsoc_testbench work.glbl -f command/isim_commands.def -o test.exe

here is the result.

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Running: /opt/Xilinx/14.4/ISE_DS/ISE/bin/lin/unwrapped/fuse work.orpsoc_testbench work.glbl -f command/isim_commands.def -o test.exe
ISim P.49d (signature 0xfbc00daa)
Number of CPUs detected in this system: 4
Turning on mult-threading, number of parallel sub-compilation jobs: 8
Determining compilation order of HDL files
Analyzing Verilog file "[...]/verilog/cfi_ctrl/cfi_ctrl.v" into library work
Analyzing Verilog file "[...]/verilog/dbg_if/dbg_cpu_registers.v" into library work
[...]
Analyzing Verilog file "[...]/xilinx/atlys/bench/verilog/orpsoc_testbench.v" into library work
Starting static elaboration
WARNING:HDLCompiler:189 - "[...]/ethmac/eth_fifo.v" Line 245: Size mismatch in connection of port . Formal port size is 4-bit while actual signal size is 5-bit.
WARNING:HDLCompiler:189 - "[...]/ethmac/eth_fifo.v" Line 246: Size mismatch in connection of port . Formal port size is 4-bit while actual signal size is 5-bit.
WARNING:HDLCompiler:189 - "[...]/ethmac/eth_fifo.v" Line 254: Size mismatch in connection of port . Formal port size is 4-bit while actual signal size is 5-bit.
[...]
ERROR:HDLCompiler:1654 - "[...]/atlys/rtl/verilog/clkgen/clkgen.v" Line 149: Instantiating from unknown module
ERROR:HDLCompiler:1654 - "[...]/atlys/rtl/verilog/clkgen/clkgen.v" Line 157: Instantiating from unknown module
ERROR:HDLCompiler:1654 - "[...]/atlys/rtl/verilog/clkgen/clkgen.v" Line 184: Instantiating from unknown module
[...]
ERROR:Simulator:778 - Static elaboration of top level Verilog design unit(s) in library work failed

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What i suspect is that :
the project file "orpsoc_sim.prj" contain path to some unjustified verilog files.

My questions are :
- how to know wich files do i need to add into the "project file" ?
- is there any other tutorials to run simulation of openrisc using xilinx isim simulator ?

thanks in advance for the reply !

---

i am using the ubuntu precompiled openrisc virtualbox.
i am using Xilinx 14.4
i try to understand how to compile, test, run and use linux with openrisc on atlys platform.

hey,

The simplest method.

For Synthesis:
1) make a new project
2) find out the top module and add to the project in the PWD.(working directory)
3) synthesis it, then it will give you error saying which all modules are needed.
4) Add all of it one by one, and it will get synthesized after adding all.


after synthesis is done, click the simulation button
1) Add the test_top module.
2) Add all the files specified in test_top
3) simulate it