Hi,
I designed 4-way set associative DATA cache of or1200 processor. When I am running existing test cases on new rtl (instead of direct mapped, I used 4-way cache) so all are getting fail except or1200-simple.
I am comparing executed.log for 4-way cache & direct mapped cache.
I found in case of 4-way after executing "0x00001474" address, next it is executing "0x00001500" but in case of direct mapped cache after executing "0x00001474" address, next it is executing "0x00001478",,why?? Also "0x00001474" is l.sw instruction.

Also I found at address "0x0000146c" onebit of status register is 'x',,its previous instruction is "0x00001468" (l.lwz)..
I hope I am clear with the problem.
Please help me out. Suggest your solution.
Thank you.

It's close to impossible to give you any suggestion with the information you have given.

1) We have no idea what your changes are, obviously they are causing the problem.
2) We have no idea what test you are referring to with "0x1474" and "0x1500",
and even if you did, it would be impossible to conclude anything from it without
seeing the complete disassembly (and that might not be enough neither).
Even if that's where things *seem* to go wrong, you can't be certain that there isn't
something that has happened earlier that cause that to go wrong.

So, if you want help debugging why your code doesn't work, you need to show us your code.