There are no Altera directory in orpsocv2/boards.

Is it difficult to using Openrisc on ALtera DE boards? Will it take a lot of time?

If you know some tutorials about this, please let me know.

Thank you.

Hi,

What kind of board do you have ? There is may be an existing port....

Franck.

I'm using DE3.

Hi,

Probably a little late to answer but I actually used this exact board when doing development with OpenRISC in 2009-2010 for a research project. There is no directory for DE3 true, but if you can figure out how to connect the pieces together and make the GNU toolchain work, you should have a working system with minimal (read 4-6 months) effort. Here are the opencores.org cores that were used in my project:

-OpenRISC 1200
-Ethernet 10/100
-I2C core (8 bit wishbone interface needs manual adaptation, SPI better maybe?)
-UART
-Wishbone 8 master, 8 slave interface (I forget the name)

Additionally, I created the following components from scratch:

-single wire bus (custom protocol)
-boot loader (copy program from I2C memory to on-chip memory, then jump to initial address)
-memory interface to use FPGA memories
-custom GPIO
-top-level file

It took me about 4 months to figure everything out and 2 more months to fix all the errors, but I didn't need to dig into the internals of any of the provided cores to get a decent working system. I completely ignored the JTAG programming system so can't comment on its effectiveness with any authority but the literature online suggests that it works well so you might try it instead of an I2C/SPI off-chip memory. To test booting, download one of several I2C/SPI memory verilog models that are available from several of the companies that manufacture them.

You can also try modifying the minsoc project which includes all the components in a single, ready-to-build project. Forget looking inside the OR1k2, eth, etc. cores and focus primarily on how the cores connect together through the Wishbone interface. Also, you need to figure out how you're going to boot your system, and the addressing for memory mapped I/O, and how to run the program. Also, developing your own, custom GPIO verilog core for connection to the wishbone bus is a good learning experience if you haven't done it yet. Also, a program to convert a a compiled program to a verilog vector map is required.

If you can write a program in C to use your custom GPIO interface, load the program's bit vector into Verilog, copies the program from the serial RAM to on-chip RAM, then runs the program and the GPIO pins operate, you have a working design that's ready for testing. Monitor the Wishbone bus so you can figure out how memory is being copied around by your boot loader, the processor, and other bus masters. It helps a great deal during debugging.

This may not be the best way or easiest way to do it, but it worked for me. Best of luck!

James