Hi, I am new to OpenRISC and I have some major troubles during debug of the toy program on it. I am using Nios II development board with Cyclone II and with 2M of external SRAM memory on board.

If I use default compilation (for or1ksim), physical memory range does not comply with the program, which leads to corresponding reactions from the system: as stack is out of physical memory, it looks like it overlaps with something else and during execution of the program it corrupts itself and everything fails. At the same time small toy programs run almost perfectly (excluding some debug troubles, as program sometimes gets stuck on breakpoints).

So I made changes to *.s file and compile accordingly to memory size of my board:

_board_mem_size: .long 0x200000

It indeed worked, as I can see new values of memory size and board frequency after program load. But in this case even for the simplest program after start of it I get "Remote failure reply: E01" in gdb and "Error while reading all registers: 'CRC mismatch'" in adv_jtag_bridge. Another type of filure is when the program goes to the end of the memory range, so I need to reconfigure Cyclone and/or reset SRAM with program.

How can I start using and debugging OpenRISC on my board? I searched in mailing list and on forum, but couldn't find any clues. I would appreciate any help with my problem.

Here are tools that I use:
or32-elf-gcc -g led_test.c -o led_test -Xlinker -Map -mboard=niosc2
or32-elf-gdbtui
./adv_jtag_bridge -b ~/.bsdl -l 0:4 -c 8 usbblaster

In attachment is a code of my toy program.

Additionally, as I am a first-time gdb user, it would be great, if someone could advise me a more convinient way of debug than gdbtui in console mode, which I use now.

Regards,
Olga

Hi

So your problem is mainly with debugging the board and GDB?

What RTL are you building from? ORPSoC?

Julius

Hi, Julius,

> So your problem is mainly with debugging the board and GDB?

Yes, the main problem is with debugging. However, occurrence of the problem somehow correlates with changes of target memory size during compilation.


> What RTL are you building from? ORPSoC?

I used following sources from OpenCores svn:
[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] - Rev 858
[/] [adv_debug_sys/] [trunk/] [Hardware/] [adv_dbg_if/] [rtl/] [verilog/] - Rev 69
[/] [adv_debug_sys/] [trunk/] [Hardware/] [jtag/] [tap/] [rtl/] [verilog/] [tap_top.v] - Rev 69
[/] [wb_conmax/] [trunk/] [rtl/] [verilog/] - Rev 8

additionally, I used custom SRAM board memory controller and led driver.

Is ORPSoC, which you mentioned, located at [/] [orpsoc/] [trunk/] - Rev 1? I couldn't find any files there, is it OK?