Hi, I have some questions about simulation

1.
According to orpsoc.pdf(p.13), we can run a simulation from the sim/run path.
According to orpsoc.pdf(p.42), we can run a simulation from the boards/xilinx/atlys/sw/run path.
What is the difference between them?

2.
I'm reading a tutorial and following the instructions.
I have problems when I use ISim.
http://www.rte.se/blog/blogg-modesty-corex/simulating-orpsoc-using-isim/2.4

The main problem is that:
The ISE I used is under webpack license, and ISim is very slow.
As a result, I go back to orpsoc.pdf and I want to use Icarus Verilog instead.

cd boards/xilinx/atlys/sim/run
make rtl-tests

But some errors occur.

3.
How to use Icarus Verilog instead so that I can do the same in the tutorial?

Hi,

1.
According to orpsoc.pdf (4.2.3), the simulation from the sim/run path is a RTL simulation of the reference design.
According to orpsoc.pdf (8.4 ), the simulation from the boards/xilinx/atlys/sw/run path is a RTL simulation of the specific Atlys design (not RTL of the reference design). It will take verilog files from modules situated on reference design except if there is a specific module specially configured for Atlys board. then it will simulate.

2.
I also want to use Icarus Verilog to simulate the board specific design.
the following error are typically due to the lack of modelsim. if you have the chance to have it(i don't have this chance), install it and run again :
/bin/sh: vlib: command not found
make: *** [work] Error 127

3.
I don't think you can use Icarus Verilog instead because some part of the Verilog is specific to Xilinx. but i can be wrong.

4.
I also followed the tutorial from http://www.rte.se/blog/blogg-modesty-corex/simulating-orpsoc-using-isim/2.4
but i didn't succeed to make the first step title "Setting up the simulation project file".
How did you manage to do it ?

5.
You can contact me by mail at vandendriessche.pierre@gmail.com to exchange on the subject to run and simulate openrisc on Atlys platform.

About the first step title "Setting up the simulation project file": If my memory serves me right, I need to add a line to , because one of RTL Verilog file is not included. I forget what file did I add. Please see the error message to figure out.