Hi,

I've got an orpsocv2 running on an FPGA board. I can connect to the target, load
programs and debug using or_debug_proxy and GDB. So far, so good. As i want to
verify a custom implementation of or1k which has no debug interface yet, I built the orpsoc without CPU debug interface (but still with or1200) to see if debugging is
possible only accessing the WB bus. My first attempt:

Connecting to OR1k via USB debug cable

Initialising USB JTAG interface
JTAG ID = a188a928
Stalling OR1K CPU0
Communication error. Retrying
Resetting or1k
Resetting or1k
Resetting or1k
Stalling or1k
or1k should be stalled

OK, there is a switch for or_debug_proxy:
'-b Bus access only - do not attempt to talk to the CPU'

Things looked more promising now:

Connecting to OR1k via USB debug cable

Initialising USB JTAG interface
JTAG ID = a188a928
Waiting for gdb connection on localhost:5000
Press CTRL+c to exit.

After starting up GDB and trying to connect (target remote ...):

Remote debugging from host 127.0.0.1
Communication error. Retrying
Error read from register
Resetting or1k
Resetting or1k
Resetting or1k
Stalling or1k
or1k should be stalled

So, my guess is when trying to hook up GDB or_debug_proxy wants to talk to the
CPU even if I tell it not to talk to the CPU. Does anyone have insight into
this and can tell me if it should generally be possible to debug an orpsoc only
with wishbone bus access?

Thanks for any help,

Mikkl

OK, so i got that finally solved myself and if someone runs into similar trouble:
What I initially did was commenting out two defines in 2 different files:

- in or1200_defines.v:
//`define OR1200_DU_IMPLEMENTED
- in dbg_defines.v:
//`define DBG_CPU0_SUPPORTED

The thing is that the second define 'DBG_CPU0_SUPPORTED' is actually needed because the debug unit 'dbg_if' needs a way to at least stall the CPU so the debug wishbone interface can act.
So, for my custom CPU implementation I just needed to include the 'or1200_du' unit in my design and make use of the 'du_stall' signal.

Regards, Mikkl