Although it's insignificant, but still a typo :)

Index: rtl/verilog/or1200/or1200_alu.v
===================================================================
--- rtl/verilog/or1200/or1200_alu.v (revision 864)
+++ rtl/verilog/or1200/or1200_alu.v (working copy)
@@ -149,7 +149,7 @@
assign carry_in = (alu_op==`OR1200_ALUOP_ADDC) ?
{{width-1{1'b0}},carry} : {width{1'b0}};
`else
-assign carry_in = {width-1{1'b0}};
+assign carry_in = {width{1'b0}};
`endif

`ifdef OR1200_IMPL_ALU_COMP3