Hello everyone, sorry for my previous topic related with 3 clock cycle latency. I realized that the problem was that the instruction cache was disabled, therefore I saw each and every instruction with latency. Can you please tell me how to ENABLE the instruction cache, I checked it on Google but I did not come up with any clear explanations and code examples. Could anyone provide that If they have?
Thx in advance!

Hi,
There is a file "or1200_defines.v". in this file there are configuration details.
You have to comment(disable) this statement : `define OR1200_NO_IC to enable instruction cache.

--Sudhanshu

Hello,
I commented out all of the statements which disabled the synthesize of IC, DC, IMMU, DMMU etc. However I still get the same result. I also have the ic_en signal on the oscilloscope and it still is LOW. I added an oscilloscope screen showing least significant 8 bits of PC (Bus2), the opcode (Bus1), Clock (D1), ic_en signal (Bus3), and icqmem_ack_ic signal at D0.
I would appreciate if you could help me out finding the possible solution.
Thx in advance!

It's not enough to enable the instruction cache hardware, your software needs
to enable the instruction cache as well. Does it do that?

Hi,
Can you provide me with the testcase you are running, because IC needs to be enabled in both hardware & software (as mentioned by stekern). If you haven't prepared any testcase, it is preferred to write it in assembly language instead of C.
Once you are done with writing testcase, we can add patch (a piece of code) to enable IC.