Hello folks,
I am trying to simulate the OR1200 processor that I modified. I do the steps as explained below (although I don't have a bench):
http://www.minsoc.com/minsoc_faq#is_it_possible_to_debug_the_simulation_as_i_debug_the_firmware_running_on_my_board
After running the hex, starting the server, I start the or32_elf_gdb with uart.or32. However after loading uart.c I cannot proceed to the break point. The address is stuck at 0x100 after going 0x1200 for once (then i set it back to 0x100). It cannot even go a step with si.
What could be the possible reason for this?
I have the cache(s) (data and instruction) on and as you see above I use the uart.or32 version.
Can you help me?

I think adv_debug_sys does not work with Caches on. Check the second post on http://opencores.org/forum,OpenRISC,0,3509 . So, I'd start turning them off. What version of minsoc is your system based on?

I use 1.0 of MinSoC. So I assume there is no chance that I can see the simulation of the system where I don't get memory read latency...